EE
421L Lab 4
Authored
By Alan Fortes
on October
5, 2014
fortesa@unlv.nevada.edu
Photos
and html file directory
Part 1:
The prelab
Part 1A: Preliminary steps
1st:
Be sure to back
up all of your work from the course.
2nd:
Read
through the entire lab
before doing the prelab!!!
3rd:
Go through tutorial 2. Webpage guide here
and video guide here.
NOTE:
For the simulations that you perform for this lab:
The body of ALL your NMOS
devices must be tied
to ground, the p-substrate.
The body
of ALL your PMOS devices must be tied to a vdd! of 5 volts.
Part 1B: Creating an NMOS
schematic and layout for simulating transistor IV curves
1st:
Create a library called Tutorial_2, and a schematic cell view called
NMOS_IV.
Create an instance of an NMOS transistor by pressing the
i key, and selecting in the component browser NCSU_Analog_parts, and
nmos.
The length of the transistor mus be 600 nanometers, and the
width, 6 micrometers. After configuring the transistor's
specifications, place it on the schematic.
2nd:
Add inOutput direction pins, as seen below, to the corresponding areas.
The end result is seen below.
3rd:
Create
a symbol for the schematic view by clicking create, cell view, and from
cell view. Make sure that the library name is Tutorial_2 and the cell
name NMOS_IV.
If Virtuoso asks you where to put the pins, it
doesn't matter where you put them, for now. After the schematic
creation field opens up, delete the contents. Select each pin and press
q.
Select the all selected from the ly to drop down menu, and
value in Display drop down menu. Draw a MOSFET as seen below.
4th:
Create
a new cell view by going to file, new, and cellview, be sure to select
schematic from type, called sim_NMOS_IV. Instantiate an instance of the
symbol you created by pressing the i key and going to your Tutorial_2
library. Set up the symbol in the circuit , as seen below. Don't forget
to check and save.
5th:
Launch
the ADE and enter in the name of the model of the MOSFET. This can be
done by clicking setup and model libraries in the ADE.
Enter the line seen below, in the line seen below.
Select choose analysis and set up the dc sweep as seen
below.
To
enter the variable
of VGS, select variables, edit, and then add VGS with a value of 0. The
output to be chosen on the schematic is the drain of the NMOS. After
having done that, and what has been mentioned above, you should get
what is below. Be sure to save the state as a cell view.
Click tools and parametric analysis. Set up the settings
in the menu, as seen below. After that, click the green play button.
You should get results as seen below.
6th:
Now,
we will create a layout of the NMOS schematic previously created. In
the Tutorial _2 library, NMOS_IV cellview, create a layout cellview.
In
the layout cellview, press e and make sure the settings are as seen
below. The main features to look out for are to make sure that Pin
Names is
checked, Create and Edit are set to anyAngle, and that Stop is set to
be 10.
After
setting your configuration, as seen above, set the layout by creating
an instance of an NMOS. This can be achieved by pressing i, selecting
in the library browser, NCSU_TechLib_ami06, nmos, and layout. In the
Create Instance window, set the dimensions, as seen below.
Add the appropriate pins, including the gate and body of
the NMOS, as seen below.
DRC and extract the NMOS. The extract result is seen
below.
Be sure to run an LVS on the extracted layout, against the
schematic circuit.
7th:
Now, the extracted layout can be run.
Go to the sim_NMOS_IV schematic, and load the previously saved state.
Click setup, and environment.
Place word extracted between cmos.sch extractedand schematic.
Here is the proof the extracted view being used to run the simulation.
Here is the end result.
Part 1C: Creating a PMOS
schematic and layout for simulating transistor IV curves
This
part of the prelab will lack a narration due to it being similar to the
creation of the NMOS, except for areas that differ enough to warrant
commentary.
The width of this PMOS will be 12 microns. The body of the PMOS will
have a pin, rather than being tied to ground.
The ADE and parametric tool configuration of the PMOS will be exactly
as the ADE NMOS, with
the exception that the output will be the source instead of the drain.
Part 2:
The main lab
Part 2A: Creating schematics
for simulating transistor IV curves
I will now create 4 schematics and 4 simulations, as described below:
A
schematic of a 6 micron by 0.6 micron NMOS transistor with a VDS that
goes from 0 to 5 volts in 1mV steps, with VGS varying from 0 to 5 volts
in 1 volt steps.
A simulation of this schematic plotting the current
of the drain, ID, against the voltage across the drain and
source,
VDS, showing the change for every instance of VGS.
A
schematic of a 6 micron by 0.6 micron NMOS transistor with a VDS fixed
at 100mV, with VGS varying from 0 to 2 volts in 1mV steps.
A
simulation of this schematic plotting the current of the drain, ID,
against the voltage across the gate and source, VGS.
A schematic of a 12 micron by 0.6 micron PMOS transistor with a VSD
that goes from 0 to 5
volts in 1mV steps, with VSG varying from 0 to 5 volts in 1 volt steps.
A simulation of this schematic plotting the current of the drain, ID,
against the voltage across the source and drain, VSD, showing
the
change for every instance of VSG.
A
schematic of a 12 micron by 0.6 micron PMOS transistor with a VSD fixed
at 100mV, with VSG varying from 0 to 2 volts in 1mV steps.
A
simulation of this schematic plotting the current of the drain, ID,
against the voltage across the source and gate, VSG.
All
NMOS devices will have their bodies tied to ground, and all PMOS
devices will have their bodies tied to a vdd! of 5 volts.
Schematic and Simulation number 1:
Here is the schematic for simulation number 1. The body of the circuit
is at ground,
Vgs is set as a variable for parametric analysis, and Vds is set to be
0, as it will be swept from 0 to 5 in 1mv steps.
Here
is the output of the simulation of the circuit, where ID is plotted
against VDS.
Each curve represents an instance of where VGS is
increased by one volt. Red is when Vgs is 0 volts, and purple is when
VGS is at 5 volts.
Schematic and Simulation number 2:
Here is the schematic for simulation number 2. The body of the circuit
is at ground,
VDS is set to be 100 mV and VGS will be swept from 0 to 5 volts, in 1mV
steps.
Here
is the end result. The fact that VGS is being increase shows how the
gate acts as an electronic valve, allowing the flow of electric
current, when electromotive force is applied.
Schematic and Simulation number 3:
Here is the schematic for simulation number 3. The body is tied to a
common node being fed 5 volts.
This
is the current flowing through the drain. Since the drain is where
current is being measured from, the result is negative, but still
correct, quantification wise.
Schematic
and Simulation number 4:
Here is the schematic for simulation number 4. The body is tied to a
common node being fed 5 volts.
Here is the end result. The fact that VSG is being increase shows how
the gate acts as an electronic valve, allowing the flow of electric
current, when electromotive force is applied.
Part 2B: Creating NMOS
layouts, with probe pads
Here is the layout of an NMOS, with probe pads attached to the 4
terminals.
Here is the close up of the NMOS, showing its dimensions and how the
DRC shows no errors.
Here is the extracted view, show how the layout registers as an NMOS.
Here is the corresponding schematic.
The corresponding schematic is LVS checked against the extracted view
to verify the net lists match; they do match.
Part 2C: Creating NMOS
layouts, with probe pads
Here is the layout of an PMOS, with probe pads attached to the 4
terminals.
Here is the close up of the PMOS, showing its dimensions and how the
DRC shows no errors.
Here is the extracted view, show how the layout registers as a PMOS.
Here is the corresponding schematic.
The corresponding schematic is LVS checked against the extracted view
to verify the net lists match; they do match.
Part 3:
Backing up my lab.
In order to ensure that my lab is not lost to eternity, I zip up the
enter contents of my lab, and email it to myself.
Here, I email the zipped directory to myself.
