EE 421L Digital Integrated Circuit Design - Lab 6

Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder

Author: Abel De La Torre
Octover 20th, 2014
delatorr@unlv.nevada.edu

Pre-lab work

• Back-up all of your work from the lab and the course.
• Go through Cadence Tutorial 4 seen here.
• Read through the lab in its entirety before starting to work on it

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• Draft the schematics of a 2-input NAND gate (Fig. 12.1), and a 2-input XOR gate (Fig. 12.18) using 6u/0.6u MOSFETs (both NMOS and PMOS)

6u/0.6u  schematic


This is the coresponding draft of the  0.6 by 6u  nand gate  showing the DRC trst and showing no errors found.



This is the extracted view of the layout of the previes pic, and LVS test is implemented to check the schematic vs  extracted , and it shows a net-list match.



Niow, a symbol of a NAND gate is created and its displayed below



The following is the schematic of an XOR gate of the 6u by 0.6u  showing all the Nmos and Pmos components.



The following displays th elayout view of the 6u by 0.6u  XOR gate.  The Layout is is tested for erros using the DRC feature and as you can see it shows no erros.



Now, the extracted view of the 6u by 0.6u XOR gate is displayed .  The extracted view is LVS vs the schematic and it shows a net list match.



Now, we can creat a symbol for the XOR gate



The following is a  the schematic of  the nand and xor gates and the input and output is tested below.  The schematic is cheked and saved showing no errors.



Now we show the out put of the gates in the previews schematic.  The outputs for the nand gate show 1 as an output  except  when when a=1 and b=1.  the Xor gate shows  an output of 1 when a=1 and b=0. Also ithe Xor gate shows an output  a=1 and b=1 the output is 0 and similarly if a=0 and b=0 the output is also 0.



The following, is the implementtation of a full adder.  WE start by showing the display of the schematic below.



As with the previews schematics, a symbol is created ans displayed below.



The follwoing shows the schematic of a full adder displaying the previewsly created symbol that will be use several times in the future.



The following simulation shows the waveform of the full adder showing every element within the symbol.



Now, display the coresponding layout of the of the full adder schematic .  



After the layput is DRC and shows no errors, the extracted view is displayed  next. An LVS test is implemnted to test schematic vs extracted and it shows a net list match



Compress the lab 6 folder and get it ready for email



Email the lab6 folder to yourself to ensure a back up and not lose data.

These cells are located in directory call lab6_AD.zip