Lab 7 - EE 421L

Authored by: Medhanie Petros

E-mail: petrosm@unlv.nevada.edu

Date: 11/1/2013

Lab description

1.  Go through the tutorial_5 . Learn how to use the buses and arrays in circuit simulations. Then design a ring oscillator and simulate it.

2. Follow the lab7 descriptions to use the buses and arrays in the design of inverters, muxes and high-speed adders.

3. Backup the Lab report and upload it to the CMOSedu.com for the future study and discussion.

How to use buses and array command:

Open a new cell and copy a 10/2 inverter in it. Go to Edit--> Array or press F6 to use the array command. Then set the repeating numbers and the space between each icon. 

Next, open a new cell and put one inverter again in it. Press Q (key-binding, if no, press ctrl+I) to edit the node properties of the inverter icon. And name it to inv[3:0] that means you have 4 inverters in the one icon.

Then go to the component tab and choose the bus symbol, and then right click the other place to make a wire as buses of inputs and outputs. And then put the input/output off-page and connect them to the buses. Don't forget the name the exports as seen below.

Pre-work Tutorial_5:

Go through the tutorial_5 learning to use the buses to design the ring oscillator. 

Simulate the ring osillator

LAB7 Design:

First, make the schematic of a 8-bit inverter, then two different simulation are shown as below. One is without load, 

and the other is that several outputs has different capacitive loads.

Designning of the 8bit NAND, NOR, AND and OR gates. It is similar as you did in the above invertors.

The NAND GATE

The NOR GATE

The AND GATE

The OR GATE

The following fig. is one of the four 8-bit shows how to checking the logic function

they are all similar. Example lets take a look to OR gate

wave form

The schematic of 2-to-1 DEMUX. To check the demux function, you can simulate it, and when CLK is high, the A signal (high signal) will be sent to the output. 

waveform

To design the 8bit demux use bus, then use LTspice and IRSIM to simulate the circuit providing different frequency clock signal and get the different output result. 

Desgin the high-speed full adder. W=6, L=2 of the MOSFETs, and 

the layout design. And pass DRC, ERC, and NCC.

Using buses to design the 8-bit full adder look as following fig.

Then layout, and make sure it pass's DRC, ERC, and NCC.

Backup the work zip it and email it to yourself.

.jelib file

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