Lab 3 - EE 421L
1. Pre-lab work
How to make a 10k n-well resistor layout after finishing the schematic part in Lab1.
We need do first, go to Cell >>> New Cell then name the group of cell to R_divider then enter;
Then select the N-well resistor node in the components tab
Use
Ctril+I >>> to set the
size of the resistor as below, L=187.5 W=15 and a resistance of 10k.;
To perform a design rule check Press F5 or use Tools >>> DRC >>> Check Hierarchically. There is no errors and no warnings in the Electric Message.
ERC is to verify that the p-well is
always connected to ground in C5 process as used in the tutorial.
To Setup the ERC well check we neet to go to Preferences >>> Tools;
Press W or tools >>> ERC >>> Check Wells to run the well checker on the resisotr layout reporting some errors.
If there are errors this how to remove those errors; we don't need to check N-well connect to VDD. So we go back change the settings. Running the Well checker again.
To make N-well resistor node, a small variation of the resistor form tutorial 1 was used. The desired resistance value is 10k. We can compute the value of the resistor as a function of the dimensions of length, width, and the sheet resistance of the process.
Resistance = Sheet Resistance * (Length / Width)
It is determined that suitable dimensions are a length of 187.5 and a width of 15.
Layout design of the resistor divider, the top resistor of its rightside and right click the down resistor rightside for using metal1 to connect them, and use the left-right mouse click to design the layout as shown below
To increase the width of the metal 1 Arc to match the connection of the N-well resistor.
Using the layout, the following fig shows that how to setup a similar layout to the schematically. The resistors are aligned vertically with pins for input, output and grn (grownd).
After you do you all work be sure to back up all your works by right click on the folder you are working on and send to >>> zipped folder., then send it to your email.
