Lab 7 - ECE 421L 

Authored by Stryder Loveday

loveday3@unlv.nevada.edu

October 18, 2013 


In this lab we will be using beses and arrays in conjuncion with inverters, muxes, and high-speed adders.  Prior to this lab, Tutorial 5 should be reviewed, and can be found here.  Remember to back up all work done, should anything occur.  Future projects will be able to use many of the circuits created today.

To begin, we will create an inverter using CMOS, as we did in the previous lab.  The sizes are 20/2 for PMOS and 10/2 for NMOS.  Create an icon for the device.

To create an array, change the end of the object name to have numbers in brackets, separated by a colon.  For example, ending the object name with [7:0] will create an array of eight inverters, each referred to as 0 through 7.

Once the properties have been changed, we want to connect the inverters to a circuit.  To work with arrays, we use a bus.  A bus is essentially multiple arcs that will connectcorresponging arrays together.  To begin, select the bus tool.

We will connect the inverter array to the bus using exports, as we have done before.  Export the off-page pins using the same [7:0] numbering we have used for the inverter.

To connect a bus to a wire, we use a junction.  The junction allows us to change the sizes of the bus.  In this example, we will be using it to connect a single arc input to all eight bus connections.  We will be testing the inverters on different loads, using identical inputs but different outputs.  

As we can see, we treat each segment of the bus as its own node.  In this situation, they are all identical as there is no load, the inputs and outputs to all eight inverters is identical.  Lets try connecting different loads to a few of the bus segments.

To connect to a bus segment, create a wire arc, and name it with a number at the end, for example out[0].  Once named, this can connect directly to the bus, and will be connected to the 0 segment.  We will run a simulation below.




As we can see, the inverters can have a difficult time driving large capacitances, and we will see this is true of most logic gates.  As speed is an important aspect of design, and the gates of other CMOS devices are capacitive loads, care must be taken to not overload the circuit.

Using the same method, we will create an 8-bit version of the NAND, NOR, AND, and OR gates.  We will simulate them independantly and then as a signle schematic.







There will be additional information added as this lab is completed.  My apologies for not having it finished so far, I got distracted by the project.

A link to my .jelib file is located here.

This concludes the Lab 7 report for EE 421.  Please direct any comments or suggestions to Stryder Loveday, at the e-mail address listed above.

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