Lab 4 - EE 421L

Authored by: Yun Lan

Email: lany3@unlv.nevada.edu

Date: 9/27/13


Lab description

In this lab, we will draw schematics for a NMOS and a PMOS. We will also draw corresponding layouts fot these schematics. After these schematics and layouts for NMOS and PMOS are finished, we will simulate them by generating the simulation cells for NMOS and PMOS we drew.


First, draw the schematic for a NMOS. Use the the NMOS as shown and set a spice model for this NMOS.

Add three "Off-Page" nodes and a ground. Also, change the width of NMOS to 10 and change the model name to NMOS.

Connect the off-page nodes to the NMOS and export them.

After the schematic is done, do a DRC to see if there is any error or warning.

The steps for PMOS schematic are similar to NMOS schematic and here is the schematic for PMOS.

And do a DRC for this schematic.

Next, generate a layout for this schematic: View -> Edit Layout View.

Draw the layout by following Tutorial 2. Set the spice model for this NMOS to NMOS.

Change the width of NMOS, N-Actives, and P-Well. Then connect all parts together. When connecting the P-Well to the ground, you may want to change the width and End Extension of the metal 1 arc that connected with P-Well if the width is too large.

Make some input nodes for this NMOS by connecting with metal 1 and exporting them as D, G, S, and gnd. 

Do the DRC and NCC to verify this layout.

Both DRC and NCC are completed without errors.

The steps for PMOS layout are similar to the NMOS layout. Change the width of the PMOS to 20.

Connect all parts together and export the nodes as D, G, S, and vdd just like I did for NMOS.

Again, do the DRC and NCC to verify the layout for PMOS.

Everything is fine.

Now, create simulation cells for the schematics of NMOS and PMOS. The spice code can be added by clicking Misc. -> Spice Code.

Here is the simulation result for NMOS.

The simulation cell for PMOS.

Here is the simulation result for PMOS.

The schematic of NMOS can be used by the simulation cell by dragging the schematic for NMOS to this simulation cell as shwon.

We can see the detail of the NMOS by click One Level Down as shown.

Backup...

The Electric library for lab 4 can be found here.


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