Lab Project - EE 421L
Authored
by Larin Lamoreaux
November 8, 2013
lamorea3@unlv.nevada.edu
Project Goals:
1. Desgin an ALU that can perform AND, OR, A+B and A-B. Where A and B are 2 8bit words.
2. By Novemeber 8th have the schematic layed out along with simulations.
3. By Nobember 22nd have the layout and layout simulations complete
Project Report:
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