We will make and implement an 8bit inverter using buses.
First
we grap our regular 1 bit inverter. Next rename the invert to
inverter[7:0] this command implies we now have an array of 8
inverters
![](Lab7%20Pictures/fig3%20Regualr%20inverter%20icon.JPG)
Next
add buses to the inverter and name the buses in[7:0] and out [7:0] Now
we have an array of 8 inverters with 8 inputs and outputs
Finally build an icon
![](Lab7%20Pictures/Fig7.JPG)
Here is the the icon and the simulation to show the 8bit outputs
Simulation of Vin versus the all 8bit outputs
![](Lab7%20Pictures/fig8.JPG)
Here we will test the ouptus with a few capacitors.
![](Lab7%20Pictures/fig9.JPG)
Sim results shows that the largest capacitor switchs the slowest as expected.
![](Lab7%20Pictures/Fig10.JPG)
\
Here I designed a 8bit AND, NAND, NOR, OR , and Inverter.
![](Lab7%20Pictures/Fig11.JPG)
Here is the AND and NAND sims. Notice the output signals are inverse as expected.
![](Lab7%20Pictures/Fig12.JPG)
Here is the OR and NOR sims. Notice the output signals are inverse as expected.
![](Lab7%20Pictures/Fig13.JPG)
Next we will make a DMUX gate.
![](Lab7%20Pictures/Fig14.JPG)
Here is the Icon and Sim. We can see when "Vs" is low the output fallows "Va" and when low the output fallows "Vb".
![](Lab7%20Pictures/Fig16.JPG)
The IRSIM results match.
![](Lab7%20Pictures/fig2%208bit%20Mux%20Sim.JPG)
Here is 8bit DEMUX
![](Lab7%20Pictures/Fig18.JPG)
The 8bit Sims fallows the same results as above.
![](Lab7%20Pictures/Fig17.JPG)
![](Lab7%20Pictures/fig2%208bit%20Mux%20Sim.JPG)
Demux with Z input
![](Lab7%20Pictures/fig19.JPG)
Sims
![](Lab7%20Pictures/Fig20.JPG)
![](Lab7%20Pictures/fig1%208bit%20mux%20z%20input.JPG)
Next we will make a 1 bit full adder
![](Lab7%20Pictures/Fig22.JPG)
Full adder layout
![](Lab7%20Pictures/Fig26.JPG)
![](Lab7%20Pictures/Fig27.JPG)
![](Lab7%20Pictures/Fig21.JPG)
Here is the sim and works as expected
![](Lab7%20Pictures/Fig23.JPG)
Here we make an 8bit adder
![](Lab7%20Pictures/Fig24.JPG)
The 8bit Adder layout
![](Lab7%20Pictures/Fig28.JPG)
8bit Adder NCC, DRC, and Well check all pass.
![](Lab7%20Pictures/Fig31.JPG)
N
![](Lab7%20Pictures/Fig29.JPG)
8bit icon and sim.
![](Lab7%20Pictures/Fig25.JPG)
A inputs
![](Lab7%20Pictures/fig4%208bit%20FA%20A%20inputs.JPG)
B inputs
![](Lab7%20Pictures/fig5%208bit%20B%20inputs.JPG)
Outputs as expected
![](Lab7%20Pictures/fig6%20%208Bit%20Sum%20Output.JPG)