Lab 6 - EE 421L
Authored
by Larin Lamoreaux
October 14, 2013
lamorea3@unlv.nevada.edu
Lab 6 Jelib file
Lab Goals:
- In
this lab we will make 3 logic gates (NAND, NOR, XOR) and use them to
build a 2 full adders made up of different combinations of logic gates.
Lab Report:
- Draft the schematic of a 2-input NAND gate (Fig. 12.1) using 10/2 MOSFETs (both NMOS and PMOS)
- Create layout and icon views for this gate showing that the cells NCC, DRC, and well-check without errors
- Icon is in the top picture in the top left corner
![](Lab6%20Pictures/fig2..JPG)
- Well, NCC, and DRC check fine.
![](Lab6%20Pictures/fig3.JPG)
- 3d view
![](Lab6%20Pictures/fig4.jpg)
- Using both LTspice and IRSIM simulate the logical operation of the gate for all 4 possible inputs
- NAND truth table
![](Lab6%20Pictures/fig6.jpg)
- LTspice Sim
- Repeat these steps for a 2-input NOR gate using 20/2 PMOS devices and 10/2 NMOS devices
- Create an icon for this full-adder
![](Lab6%20Pictures/fig8.jpg)
![](Lab6%20Pictures/fig9.jpg)
![](Lab6%20Pictures/fig10.jpg)
- Simulation
![](Lab6%20Pictures/fig11.JPG)
![](Lab6%20Pictures/fig13.JPG)
- LTspice Sim.
![](Lab6%20Pictures/fig12.JPG)
![](Lab6%20Pictures/fig31.JPG)
- Again, repeat these steps for a 2-input XOR gate (Fig. 12.18) noting that the gate will also need two inverters
- For all 12 transistors used in the XOR gate use 20/2 PMOS and 10/2 NMOS devices
![](Lab6%20Pictures/fig14.JPG)
![](Lab6%20Pictures/fig15.JPG)
![](Lab6%20Pictures/fig16.JPG)
- Simulation
![](Lab6%20Pictures/fig17.JPG)
![](Lab6%20Pictures/fig18.JPG)
![](Lab6%20Pictures/fig19.JPG)
![](Lab6%20Pictures/fig32.JPG)
- Using these gates (and 3 inverters), draft the schematic of the full adder seen below
- Create an icon for this full-adder
- Simulate, using LTspice and IRSIM, the operation of the full-adder using this icon
- Show how a full-adder can be implemented using 3 NAND gates and 2 XOR gates
- Layout the full-adder by placing the 5 gates end-to-end so that power and ground are routed
- full-adder inputs and outputs can be on metal2 but not metal3
![](Lab6%20Pictures/fig24.JPG)
![](Lab6%20Pictures/fig29.JPG)
- NCC, DRC, and well-check your full-adder layout
![](Lab6%20Pictures/fig25.JPG)
- Create another icon view and again simulate using LTspice and IRSIM
Backup LAB
![](Lab6%20Pictures/fig28.JPG)
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