Lab 5 - EE 421L 

Authored by Larin Lamoreaux
October 5, 2013 
lamorea3@unlv.nevada.edu

MY jelib file     

    

Lab Goals:

  1. In this lab we will extend our knowledge of transistors and create a smiple inverter. We will also make use of the IRSIM and ALS add simulation tools.
   
     

 

Lab Report:

20/10 PMOS/NMOS inverter schematic. Take note of the icon in the top left corner of the picture below.


 

Layout View of 20/10 PMOS/NMOS inverter. Take note of the 4 pins I exported in, out, gnd, and vdd

3D View of the PMOS/NMOS inverter

NCC, Well check, and DRC the design.

Simulation of the 20/10 inverter driving 3 capacitive loads 1p, 10p, 100f

We notice in LT Spice that there switch behavior is close to the same. Althoug if i cylced the imputs the 10p capacitor would have the largest lag.

  Schmatic of a 20/10 PMOS/NMOS inverter with a multiplyer of 5


 

Notice the difference in the layout schmatics. This Transistor layout has a 5 multiplier which mean that we have 5 20/10 transistors in parrallel. This also has the same exports as before, in, out, gnd, and vdd

Here is the Well Check, DRC, and NCC of the design

Just as before we simed the inverter with the same capacitive load



In this sim we see a sliightly fast switching speed compared to the above sim. The capacitances appear not to have an affect on the output.



Next is my IRSIMS

Notice in the simulation below that IRSIM does take into account the delay in the circuit




ALS Sims

My ALS sim look the same as IRSIM except no delays. ALS sim is good for checking input and  reaction of output signals, whereas IRSIM is good for checking input to output timming.












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