Lab 3 - EE 421L
Authored
by Larin Lamoreaux
September 13, 2013
lamorea3@unlv.nevada.edu
Lab 3 jelib file
Lab Goals:
- Create a layout view of the 10-bit DAC that we made in Lab2
Lab Report:
- Use the n-well node for the layout of a 10k resistor as discussed in Tutorial 1
- Discuss,
in your lab report, how to select the width and length of the resistor
by referencing the process information from MOSIS
- First we need to access MOSIS process information found here
- Look
at the Sheet Resistance per square above and we see that it is 800.5
ohms. Now we take resistance/Sheet Resistance per square =
10k/800.5= 12.5. Next we find minimum width for n-well material here.
On page 16 we see it is 12. We will use a value slightly bigger of 15
and times that by number of squares from above which is equal to
12.5*15= 187.5. This gives us our length (187.5) and width (15)
values which we cna use for electric.
- Use this n-well resistor in the layout of your DAC
- Here I used the n-well resister 30 times to make up a 10bit DAC
- Discuss, in your lab report, how the width and length of the resistor are measured by Electric
- Notice that the length of the reister is from pad to pad, not the overall length of the resister.
- Ensure
that each resistor in the DAC is laid out in parallel having the same
x-position but varying y-positions (the resistors are stacked)
- Here is the first few bits of my DAC showing that all resisters are "stacked".
- Inputs and outputs (exports) should be on metal 1
- You can see from my image above that all exports are on metal 1.
- DRC, NCC, and ERC your design (show the results in your lab report)
- Here is the schmatic view of my sim
- Here is the results
- Place
your final jelib in the lab3 directory, with a link on your lab report,
so the grader can examine both the layout and schematic (and
simulations)
- Last of all back all files
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