Lab

I first saved the libary link to my desktop lab2.jelib
next I opened Electric and opened a new library that I named EE421.jelib
I opened another library and browsed for the the lab2.jelib file that I saved on my desktop. I opened and save the lab2.jelib link in electric
Next I transfered the files from Lab2.jelib file to the EE421.jelib library useing the cross reference library tool as seen below

Then in the EE421 library I opened the sim_ADC_DAC(sch) file

Then I ran the sim.

You will notice in the picture above that the out signal fallows the input signal expect the output has a "stair like" appearance. This is due to the analog signal being converted into digital pulses. In the image below I separated the digital pulses and we can see that the output signal is just an addition of all the digital pulses. The more bits we use the higher the resolution we can achieve i.e. a smoother output signal.

Here I zoomed in on the LSB (B9) and we can see the minumum voltage required to trigger the DAC. Here it is about 2.5 volts.

The design of a 10-bit DAC using an n-well R of 10k

How to determine the output resistance of the DAC (answer: R) by combining resistors in parallel and series

Delay, driving a load

Ground all DAC inputs except B9. Connect B9 to a pulse source (0 to VDD) and show, and predict using 0.7RC, the delay the DAC has driving a 10 pF load

Td= .7RC= .7*10K*(10*10^-12)= 70ns

Verify the simulation results match your hand calculations

How to create an icon for your design with the exact same footprint as the 10Bit_Ideal_DAC

Click on the icon in the schematic view. Next hit ctrl+D this takes us down into the icon and we now can edit the icon.

When we are finished editing the icon we hit crtl+U which will take us back to the schematic layer. We also can add a new icon by going to the cell tab on the toolbar then scroll down to new cell. When the window pops up click on icon.

Simulations to verify your design functions correctly.

Copy the cell sim_ADC_DAC{sch} to a cell sim2_ADC_DAC{sch} and replace the ideal DAC with the one you just designed

Use the sim2_ADC_DAC{sch} to illustrate that your design works as expected.

Show what happens if the DAC you designed drives a load (both R, C, and R/C)

Driving a load of a 5k resister. Notice that the 10k resistance inside the DAC and the external 5k resister make a voltage divider. Now my output signal has an amplitude of 1.67 volts

Driving a 10pf capacitor. You will notice that the output signal is a combination of the 10K internal resistance and the 10pf external capacitor. The result is a small voltage drop and phase shift.

Driving a 5k resistor and 10pf capacitor. Now we have the voltage divider between 10k internal resistance and 5k external resistor in addition to the phase shift from the 10pf capacitor.

Explain what happens if the DAC drives a 10k load?

Then there becomes a voltage divder between the 10K internal resistor and the 10k external resistor. The output signal would then be half of the intput singal.

Discuss what happens if the resistance of the switches isn't small compared to R.

Then this will affect the resistor ratio of 2R/2R we would have a ratio of( MOSFET+2R)/2R. This added resistance, if large enough can dramatically decrease the amplitude of the output signal.