Lab

Lab 7 - ECE 421L

Authored by Fred Hathaway,

hathawa6@unlv.nevada.edu

26 Oct 2013

Lab 7: Using buses and arrays in the design of word inverters, muxes and high speed adders:

In this lab, I will be using buses and arrays to design word inverters, muxes and high speed adders.

I completed the prelab and followed tutorial 5.

After completing the prelab assignment (tutorial 5) I understood how to use the array command to create multiple instances of a device. Additionally I was able to create a bus of four inverters rather than create four separate inverters.

Below are the results of the prelab:

Below are four inverters:

Now instead of using four separate inverters, I created a bus by using arc bus tool circled in the clip below.

To create the bus high light the device and press CTRL-I to change the Name to inv[3:0]. This will define the connections of the bus. (IE: inv[3] input is b[3] and the output is bi[3]. Do the same for the bus arcs and lable them as seem below.

Next, I created a ring oscillator schematic using 11 sepatate inverters.

Below, is the same ring oscillator using inverter connected on a bus.

Layout view:

Simulation of the ring oscillator:

Lab 7:
I will be building a circuit that will consist of four inverters. We can use the schematic seen below.

Or we can make an equivalent schematic by intantiating the inverters using the array name inv[3:0] as seen below and connect them to buses and exporting names b[3:0] and bi[3:0]. This method provices a cleaner schematic especially when creating larger circuits.

Now I am going to create an 8-bit word inverter. I basically used the same building blocks above using the bus connections. Additionally, I created an icon for use in future projects.

I created an icon of the inverter.

Next is to design another schematic for simulation. I connecting a wire to the buses by using the junction "J" connection. This will allow me to connect the bus line together and call it Vin. Note that the junction is used to change the bus size. I added copactive loads on the output of three of the connections. Notice that the wires can be connected directly to the bus lines. This can only be done if the wire is named appropriately so that Electric knows what signal on the bus we are connecting to.

Below are the simulation results:
Notice that the inverter can't drive the 1pF load very quickly.

Next I created schematics and icons for the AND, NAND, OR and NOR gates.

AND array icon:

NAND gate array schematic:

NAND gate array icon:

OR gate array schematic:

OR gate array icon:

NOR gate array schematic:

NOR gate array icon:

Now I will put all of the above gate arrays together in one schematic and simulate them:

Below are the simulation results:

Next I created a 2-to-1 DEMUX.

The DEMUX schematic:

The DEMUX icon:

The DEMUX LTSpice simuation schematic:

LTSpice simulation of the DEMUX: Note that when the select V(s) is 0, the output V(z) will the value of V(b). When V(s) is 1 V(z) output will be the value of V(a). This can be verified with the LTSpice simulation seen below:

Additionally, we can use the DEMUX to function like a MUX. The input is supplied to Z and the device will function as a MUX. The results are seen in the simulation below:

The next step is to create a DEMUX array schematic with icon:

DEMUX Icon:

IRsim of DEMUX array:

The next step is to use buses to design an 8 bit full adder. Below is a clip of the schematic.

The icon view.

Next, I designed an 8-bit full adder. The biggest problem with this part is routing the devices. I found it easier to break it down into smaller parts. Do the DRC, ERC and NCC checks as you go along if you decide to design the adder in sections.