Lab 5 - ECE 421L 

Authored by Ken Adams,

adamsk5@unlv.Nevada.edu

4 October 0213 

Design, layout, and simulation of a CMOS inverter

In this lab we will design a CMOS inverter. Start by going through tutorial 3 here.

After completion of the tutorial, we will have the schematic, layout, and simulation of a CMOS inverter:

Next, we want to change this layout and schematic to use transistors with W=100 and L=50. To implement this, we will place multiple transistors in parallel. Note, that the schematic will use the spice "multiplier" option as changing the W/L of a transistor is schematically equivalent to adding them in parallel.

 For the layout of the 100/50 inverter, we will layout the transistors in parallel. The easiest way to do this is copy and paste 5 of the original layouts, removing the extra drain and source in each succession and stitch them together as follows. Make sure to export the pins, In, Out, vdd, and gnd. Notice how we connect the body of the pmos to vdd and the body of the nmos to gnd. Make sure to DRC, ERC, and NCC your design.

After designing the schematics and layouts, preform the required simulations.

Simulations:

• Using SPICE simulate the operation of your inverters showing each driving a 100 fF, 1 pF, and 10 pF capacitor

    C = 100F                                                                                                                                                   C = 100F

C = 1pF                                                                                                                                                         C = 1pF

C = 10pF                                                                                                                                                   C = 10pF

Spice produces the expected simulations. Notice that the larger transistor handles the larger load more effectively than the smaller one, as expected.

• Use ALS (Tools -> Simulation (Built-in)) to simulate the operation of your inverters driving these capacitive loads (see Electric_video_12 here)

To use the build in ALS simulator, use off-page exports so the simulator can create the appropriate netlist. 

For ASL simulations, we can combined all simulations into one schematic as follows:

C = 100f                                                                                C = 1p                                    C = 10p

As we can see, the ALS simulator only simulates the device logic. Therefore, we do not see the delay changing when the load changes.

Clearly, the spice simulation is more relevent to digital design in our case.

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