EE 420L Analog Integrated Circuit Design Laboratory Laboratory Report 3: Op-amps I, basic topologies, finite gain, and offset. | ||||||||||
AUTHOR: Henry Mesa EMAIL: mesah1@unlv.nevada.edu 02-19-2020 | ||||||||||
Laboratory Overview: This
laboratory regards the review of basic Operational Amplifier
topologies; while, introducing new non-ideal op-amps, finite gain, and
offset. | ||||||||||
Procedure: For the following experiments assume VCC+ = +5V, VCC- = 0V, and Temperature(ambient) = +25 Celsius. | ||||||||||
This Laboratory extensively uses the LM324 Low Power Quad Operetional Amplifier. The minimum and maximum
allowable common-mode voltage (VCM) is from 0V to -1.5V, such that Vcc
is not grater than 30V. The VCM are the two inputs practically at the
same pontential, with only a small offset between them. VCM = (Vin(+) + Vin(-))/2
The common mode voltage or VCM can be considered as the reference voltage on which op amp output signals ride. Generally, VCM can be found by taking the mean of VCC+ and VCC-.
The ideal closed loop gain for an inverting op amp topology can be described by the equation bellow.
Adding a DC offset to the input signal adds to the net offset of the op amp.
The maximum allowable input signal should have an amplitude less than 2.5V due to the values of VCM, VCC+, and VCC-.
C1 and C2 are decupling capacitors. Decoupling capacitors are used to even voltage out in the event of slight variance in the voltage from the power supply. Decoupling capacitors do not need to have specific capacitance values. Therefore, capacitance values such as 0.1 µF, 1000 pF, and 1 µF could all be used. When a larger decoupling capacitor is used; the startup time is longer. However, when a smaller decoupling capacitor is used; the startup time is shorter.
According to the LM324 datasheet, the op amp has an input bias current that flows in or out of the op amp’s input terminals. The flow of the input bias currents can be seen in Figure 13. This bias current is usually flows out of the op amp’s input terminals at around 20 nA. This current flows though the electrical devices connected to the input terminals. While considering the input bias current of an op amp, one might wonder how this current would effect R1 and R2. If R1 and R2 are larger the voltage drops over these resistances due to the input bias current will be larger. If these voltage drops (over R1 and R2) are too large, VCM and VM will differ. Likewise, by increasing, RF and RI, the voltage drops across these resistors become larger, due to Ohm’s Law. Also resulting in VCM and VM to differ. Thereby, adding to the net offset voltage. Offset voltage, due to bias currents, result in input offset current. | ||||||||||
Circuit 1: Build and test the following circuit . The precise balue for the 5k resistors is not important. Hand Calculations to Detail Circuit's Operation: Our Vcc+ = 5V and Vcc- = 0V. Therefore, our common mode voltage is 2.5V. The equation above show us that there will be no gain on our output. However, the op-amp will invert the signal by 180˚. Simulation: Experimental Results: Circuit 1: Input vs. Output | ||||||||||
Circuit 2: The
offset voltage can be determined by measuring the difference in voltage
between the output voltage and the Vcm voltage and the output
voltage, devided by the gain. Hand Calculations to Detail Circuit's Operation: The equation above show us that there will be a gain of 20 on the output. However, . Vcm = 2.56V and Vout = 2.52V. Therefore, the offset voltage = 2.0mV. Simulation: Experimental Results: | ||||||||||
Measured Offset Voltages : For this experiment we used 4 different op-amps to see the difference in offset.
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