Lab 9 - EE 420L
reedj35@unlv.nevada.edu
biasing and
creating an NMOS and PMOS current mirror. We will then use this current mirror
to drive
two
gate-drain connected transistors.
Prelab Work:
- This
lab will use the level=1 MOSFET model created in lab 8 and, again, the
MOSFETs in the CD4007.pdf CMOS transistor array.
- Design
and simulate the operation of a BMR that biases the NMOS devices so that
they have a gm of 20 uA/V
- Use a simple (big) resistor to VDD for the start-up
circuit (explain how the addition of a resistor ensures start-up).
- When the BMR is operating the current in the big
resistor should be much smaller than the current flowing in each branch
of the BMR
- Write-up,
similar to a homework assignment, your design calculations
and simulation results. (This will count as the pre-lab
quiz.)
- Ensure
that you show the following in what you turn in:
- Hand calculations
- Operation as VDD is swept from 0 to 10 V
- Vbiasn should
stabilize (be constant) after VDD hits a minimum value (estimate this
value of VDD assuming VGS/VSG is a threshold voltage and VDS,sat/VSD,sat
is zero).
- Vbiasp should follow
VDD after VDD hits a minimum value (show this in simulations)
- Unstable operation if too much capacitance is
shunting the BMR's resistor (see bottom of page 630)
- Comments comparing the hand calculations with the
simulation results
Hand Calculations:
In order to do the hand calculations
to characterize the BMR, I used the parameters from the Level=1 model from Lab
8.
A BMR
circuit looks like the following:
To find IREF:
and we are given a gm=20ľA/V, so we
can solve for IREF using the parameters from the Level=1 model of
the NMOS.
To find out
the value of R I need for my BMR, the voltage at the node above the resistor is
Therefore, 
If we solve for these voltages using the
square-law equation, we get:
If we
multiply R over to the left side, and pull out the common radical:
If I choose
K=4,
Experiment 1: Design and build a
BMR
- Build your BMR design and characterize
it as you did in the pre-lab (if you use two chips ensure that grounds and
VDDs of both chips are tied together).
- You expect
the BMR to become unstable if there is a large capacitance across the
resistor, such as a scope probe (important), so care must be
exercised
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VDD (V) |
Vbiasn (V) |
Vbiasp (V) |
ID (ľA) |
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0 |
0.007 |
0.005 |
0 |
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1 |
0.243 |
0.0107 |
0 |
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2 |
0.5 |
0.594 |
0.546 |
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3 |
0.837 |
1.66 |
0.664 |
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4 |
0.928 |
2.57 |
0.776 |
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5 |
0.962 |
3.6 |
0.874 |
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6 |
0.984 |
4.64 |
0.958 |
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7 |
1.003 |
5.57 |
1.05 |
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8 |
1.02 |
6.62 |
1.13 |
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9 |
1.04 |
7.64 |
1.22 |
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10 |
1.05 |
8.64 |
1.30 |
As can be seen above, when we compare the simulated values to the experimental
values, they are very close. This validates the parameters for the Level=1
model. Since the parameters are not perfect, the values will not
match exactly. The method for measuring the drain current was by using a 20k
resistor at the
drain of the MOSFET, measuring the voltage drop across the
resistor, and dividing by the resistor value. This had to be done due to the
current being so small
that the multimeter could not accurately display values below 1ľA.
According to the experimental plots above, the BMR starts working at around VDD
= 2-3V.
When first modeling the MOSFETs in LTSpice,
the bias voltages were not behaving as expected. I did more adjustments to the
parameters in the Level=1
model and came up with the simulation waveforms above.
Experiment 2: Current Mirror
- Use your BMR to bias, and thus
create, a:
- NMOS
current mirror
- PMOS
current mirror
- Measure how the current varies through
each current mirror as the voltage across the mirror changes.
- Of course,
the current in the NMOS (PMOS) current mirror goes to zero as the voltage
on the drain of the output device moves towards ground (VDD)
NMOS Current Mirror
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PMOS Current Mirror
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VDD (V) |
ID (ľA) |
NMOS Current Mirror ID (ľA) |
PMOS Current Mirror ID (ľA) |
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0 |
0 |
0 |
0 |
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1 |
0 |
0.009 |
0 |
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2 |
0.546 |
0.285 |
0.325 |
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3 |
0.664 |
0.435 |
0.480 |
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4 |
0.776 |
0.570 |
0.640 |
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5 |
0.874 |
0.705 |
0.815 |
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6 |
0.958 |
0.865 |
1.03 |
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7 |
1.05 |
1.02 |
1.30 |
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8 |
1.13 |
1.20 |
1.57 |
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9 |
1.22 |
1.38 |
1.94 |
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10 |
1.30 |
1.58 |
2.39 |
According
to the simulations and experimental results, the current mirrors behave as
expected. However, the NMOS current mirror experimental
values are
about half as much as the simulations. This could be due to human error or
improper measurement of the current.
Experiment 3: Drive two gate-drain
connected transistors using the current mirror
- Using these current mirrors
drive two gate-drain connected transistors
- For the first
experiment use the NMOS current mirror to drive two PMOS gate-drain
connected devices.
- Use the
voltages on the gate-drain connection of the two devices to bias a cascode current mirror (characterize this mirror as
before)
- For the
second experiment switch, that is, use the PMOS current mirror to drive
two NMOS gate-drain connected devices.
- Again, use
these two voltages to bias an NMOS cascode
current mirror then characterize.
NMOS Current Mirror driving two gate-drain connected PMOSs
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PMOS Current Mirror driving two gate-drain connected NMOSs
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VDD (V) |
ID (ľA) |
NMOS Current Mirror ID driving 2 PMOS (ľA) |
PMOS Current Mirror ID driving 2 NMOS (ľA) |
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0 |
0 |
0 |
0 |
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1 |
0 |
0.1 |
0 |
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2 |
0.546 |
0.32 |
0 |
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3 |
0.664 |
0.465 |
0 |
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4 |
0.776 |
0.64 |
0.3 |
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5 |
0.874 |
0.84 |
0.5 |
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6 |
0.958 |
1.05 |
0.6 |
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7 |
1.05 |
1.34 |
0.8 |
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8 |
1.13 |
1.61 |
1.2 |
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9 |
1.22 |
1.95 |
1.3 |
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10 |
1.30 |
2.38 |
1.6 |
From the above
plots, the experimental measurements for the NMOS current mirror driving two
transistors do not match as well with the simulations.
There
should be no current until a little bit over 2.5V, however, there was current
measured starting at about 1V. The PMOS current mirror does behave
closer to
as simulated other than that the experiment starts showing current flow about
1V less than the simulation. This could also be due to how current
was
measured.