Lab 1 - EE 420L

Authored by Cody McDonald,

1/23/2019

e-mail: mcdonc4@unlv.nevada.edu

Lab description:

For this first lab simulate, and verify the simulation results with experimental measurements, the circuits seen in Figs. 1.21, 1.22, and 1.24 (use a 1 uF cap in place of the 1 pF cap) of the book. Your results should be similar to, but more complete than, the simulation results seen on pages 17 - 23. In your report, and for each circuit, show the

Circuit schematic showing values and simulation parameters (snip the image from LTspice).
Hand calculations to detail the circuit's operation.
Simulation results using LTspice verifying hand calculations.
Scope waverforms verifying simulation results and hand calculations.
Comments on any differences or further potential testing that may be useful (don't just give the results, discuss them).

Lab results:

Part 1:

For Part 1 we will be observing the input and output signals in a simple RC circuit as referenced in the figure below:

LTSpice Simulation:

Our simulation reflects the simulation in Figure 1.21:

LTSpice simulation for Figure 1.21

Oscilloscope reading:

Our oscilloscope reading very similarly matches the waveform in Figure 1.21 and our simulated waveform as well. This means that our two observations of Figure 1.21 confirmed it's operation. It can be observed that the output signal, Vout, leads the input signal, Vin, by approximately -56.2 degrees, which is close to our theoretical observation of 51.5 degrees.

Oscilloscope Reading

Hand Calculations:

Our hand calculations came within the ballpark of our measured results. The variance in our theoretical and experimental results may have been the result of the screencapture capturing the wave before the measurement tools on the oscillisope had time to obtain a better fix.

Hand Calculations for Fig 1.21

Part 2:

Part 2 will involve us observing the effects of placing a second capacitor in parallel with the resistor in this RC circuit. We can observe that the phase decreases compared to the phase indicated in part 1.

LTSpice Simulation:

Our simulation reflects the simulation in Figure 1.22:

LTSpice Simulation for Figure 1.22

Oscilloscope Reading:

Oscilloscope Reading. Note that we used a 1.8uf capacitor in place of the 2.0uf capacitor and a 1.2uf capacitor in place of the 1.0 uf capacitor.

Hand Calculations:

Our measured results similarly followed the readings we received on our oscilloscope, which confirms the theoretical results.

Part 3:

For part 3 we will be observing the input and output waveforms of an RC circuit. Here is the figure we will be referencing:

LTSpice Simulation:

We can see that our simulation also reflects the referenced simulation from Figure 1.24.

LTSpice simulation for Figure 1.24

Oscilloscope Reading:

The oscilloscope reading we obtained also reflects both the simulated and theoretical results.

Oscilloscope Reading

Hand Calculations:

Our time delay measured 755us compared to 700us theoretical. Our measured rise time of 2.1ms compared to our theoretical of 2.2ms confirms the operation of the circuit.

Figure 1.24 *note: used 33% duty cycle

Part 4:

During the final portion of this lab we observed the frequency response of the circuit in Figure 1.21. We will be analizying our experimental calculations versus the results given in the figure below. Also note that we used a 1.2uf capacitor in place of the 1.0uf capacitor due to a shortage in available electronics components in the lab.

LTSpice Simulation:

Our simualtion reflects the simulation in Figure 1.21:

Frequency Response:

The results below are our measured results after testing our circuit at various frequencies. We were unable to obtain values for frequencies 1 and 10 as the frequencies were too low to operate within the circuit. It can be assumed that these values will reflect the values derived from an approximately measured 0.96V. The magnitude and dB also reflect what we see in our simulated graphs as magnitude decreases and dB reflect a greater loss in gain as the frequency increases.

Data table measuring frequency response for Figure 1.21.

All referenced figures were captured from CMOS Circuit Design, Layout, and Simulation, Third Edition

Return to EE 420L Labs