Lab 9 - EE 420L 

Authored by Sharyn Miyaji,

Email: miyajis@unlv.nevada.edu

Today's date: Wednesday, April 19, 2017

Pre-Lab Work

• This lab will use the level=1 MOSFET model created in lab 8 and, again, the MOSFETs in the CD4007.pdf CMOS transistor array.
• Design and simulate the operation of a BMR that biases the NMOS devices so that they have a g_m of 20 uA/V 
• Use a simple (big) resistor to VDD for the start-up circuit (explain how the addition of a resistor ensures start-up). 
• When the BMR is operating the current in the big resistor should be much smaller than the current flowing in each branch of the BMR 
  
• Write-up, similar to a homework assignment, your design calculations and simulation results. (This will count as the pre-lab quiz.)
• Ensure that you show the following in what you turn in:
• Hand calculations
• Operation as VDD is swept from 0 to 10 V 
• Vbiasn should stabilize (be constant) after VDD hits a minimum value (estimate this value of VDD assuming VGS/VSG is a threshold voltage and VDS,sat/VSD,sat is zero).
• Vbiasp should follow VDD after VDD hits a minimum value (show this in simulations)
• Unstable operation if too much capacitance is shunting the BMR's resistor (see bottom of page 630)
• Comments comparing the hand calculations with the simulation results

Lab Work

Beta-Multiplier Reference (BMR)

Schematic
CD4007 Parameters
Hand Calculations
Voltage Simulation
Current Simulation

As seen in the simulations, both voltages starts to stabilize and current starts to rise when VDD is about 1V since it is the threshold voltage is about 1V.

Below are the actual measurements of the betamultiplier when it is built on the breadboard.

Compared to the LTspice simulation, Vbiasn is almost doubled, Vbiasp is not too far off, and the current is about tripled in the measurements made.  These measurements were made in the multimeter, so it may have been a factor for the measurements being off.  Another factor may have been the batch that the transistor came from were not the same.

NMOS Current Mirror

Using the BMR that was created in the first part, Vbiasn is attached to the gate of the NMOS as shown below in the schematic to create an NMOS current mirror.       

Schematic
Simulation (Current Mirror)
Simulation (Left Branch)

In the simulations, the currents flowing through the mirror and BMR are not exactly the same, which may be due to the design that was chosen for the for this experiment.

   
PMOS Current Mirror

Schematic
Simulation (Current Mirror)
Simulation (Right Branch)

Again, the currents from the mirror and the right branch do not match which may be caused from design chosen for this experiment or the parameters chosen for the text file.

The measured drain current from the PMOS current is about doubled the amount of the values of the simulation results.  This may be due to the design chosen for this experiment or the chips that were used.

NMOS Cascode

For this experiment, the PMOS current mirror that was used must be connected to NMOS cascode that are gate-drain connected.  Those NMOS cascode are gate connected with another NMOS cascode to bias the current.

Schematic
Simulation

Based on the PMOS current mirror, the expectation of the current flowing through the betamultiplier will not be exactly the same as thecurrent flowing the the cascode.

The current in the measurements are about doubled of what was simulated in LTspice, which may be caused from the design of the PMOS current mirror since it was doubled in value.

PMOS Cascode

For this experiment, the NMOS current mirror that was used must be connected to PMOS cascode that are gate-drain connected.  Those PMOS cascode are gate connected with another PMOS cascode to bias the current.

Schematic
Simulation

Again, the current flowing through the BMR are not expected to be the same as the current flowing through the PMOS cascode since it was not the same in the NMOS current mirror.

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