Lab 9 - EE 420L: Engineering Electronics II
Pre-lab work
This lab will use the level=1 MOSFET model created
in lab 8 and, again, the MOSFETs in the CD4007.pdf CMOS transistor array.
·
Design and simulate the operation
of a BMR that biases the NMOS devices so that they have a gm of
20 uA/V
o
Use a simple (big) resistor to VDD
for the start-up circuit (explain how the addition of a resistor ensures
start-up).
·
When the BMR is operating the
current in the big resistor should be much smaller than the current flowing in
each branch of the BMR
·
Write-up, similar to a homework
assignment, your design calculations and simulation results. (This will count
as the pre-lab quiz.)
·
Ensure that you show the
following in what you turn in:
o
Hand calculations Operation as VDD is swept from 0 to 10 V
·
Vbiasn should stabilize (be constant)
after VDD hits a minimum value (estimate this value of VDD assuming VGS/VSG is
a threshold voltage and VDS,sat/VSD,sat is zero).
·
Vbiasp should follow VDD
after VDD hits a minimum value (show this in simulations)
o
Unstable operation if too much
capacitance is shunting the BMR's resistor (see bottom of page 630)
o
Comments comparing the hand
calculations with the simulation results
The pre-lab work is a basic BMR design. The model I am using to
calculate this design was developed in laboratory 8 and is displayed below in
figure 1 followed by the hand calculations.
Figure 1
Below in figure 2 is the schematic and simulated results of the beta
multiplier when sweeping VDD from 0 to 10 volts.
Figure 2
As can bee seen Vbiasp Follows VDD after the threshold voltage has been
reached, and Vbiasn stabilizes after some voltage, in this case right around 2V
VDD. The big resistor tied to the drain
of the left leg ensures startup by bleeding current into the node increasing
the voltage which turns M2 and M1 on more and more as time progresses. Once a certain voltage is surpassed the BMR
will snap on function normally without much effect from the current being
supplied throght the 100MEG resistor.
Below in figure 3 is the current flowing in M2 and M1 of the circuit above
in figure 2.
Figure 3
This demonstrates that the current through each leg is roughly the
same. And fairly close to the calculated
value of 1.2uA.
Experiment 1
In this lab you may need to use two, or more, CD4007 chips
from the same production lot (see date code on the top of chip) to ensure using
a BMR to bias a current mirror is possible. If the CD4007 chips are not from
the same production lot they will not "match" so current mirrors will
not be possible.
·
Build your BMR design and
characterize it as you did in the pre-lab
·
You expect the BMR to become
unstable if there is a large capacitance across the resistor, such as a scope
probe (important), so care must be exercised
Below in figure 4 is the package layout with pin assignments demonstrating
how I wired the BMR with 3 chips
Figure 4
Table 1 below is a compiled list of voltages for Vbiasn and Vbiasp while
sweeping VDD in steps of 1V from 0 to 10 volts using the schematic above.
|
VDD (V) |
Vbiasn (V) |
Vbiasp (V) |
|
1 |
380m |
480m |
|
2 |
980m |
880m |
|
3 |
1.02 |
1.84 |
|
4 |
1.06 |
2.80 |
|
5 |
1.10 |
3.76 |
|
6 |
1.14 |
4.64 |
|
7 |
1.14 |
5.68 |
|
8 |
1.14 |
6.72 |
|
9 |
1.18 |
7.68 |
|
10 |
1.18 |
8.56 |
Table 1
As can be seen from the table above once VDD hits 2V Vbiasn stabalizes around
1.14V while Vbiasp continues to follow VDD demonstrated below in figure 5.
Figure 5
My Vbiasn experimental value is off by about 300mV.
Experiment 2
·
Use your BMR to bias, and thus
create, a:
·
NMOS current mirror
·
PMOS current mirror
·
Measure how the current varies
through each current mirror as the voltage across the mirror changes.
·
Of course the current in the NMOS
(PMOS) current mirror goes to zero as the voltage on the drain of the output
device moves towards ground (VDD)
Below in figure 6 is the LT spice schematic followed by the simulated
results.
Figure 6
As can be sen the currents in M3 and M6 are identical, the current is
mirrored in the pmos device using the bias voltage generated from the beta
multiplier circuit. The currents in M2
and M5 match as well. The resistors are
in the schematic to demonstrate how I will be measuring the current
experimentally. By placing the probes
from the multimeter in series with the resistors I can measure the current that
flows.
Below in table 2 is the experimental results for the current in each
mirrored device.
|
VDD (V) |
NMOS Id (uA) |
PMOS Is (uA) |
|
1 |
< 0.1 |
< 0.1 |
|
2 |
0.5 |
0.4 |
|
3 |
0.8 |
0.7 |
|
4 |
0.9 |
0.9 |
|
5 |
1.0 |
1.0 |
|
6 |
1.05 |
1.05 |
|
7 |
1.1 |
1.1 |
|
8 |
1.15 |
1.15 |
|
9 |
1.2 |
1.2 |
|
10 |
1.25 |
1.25 |
Table 2
From the table my experimental results are farily close to the simulated
results although my experimental currents seem to be a little higher, this is
probably a result of the bias voltages being slightly above the simulated
values.
Experiment 3
·
Using these current mirrors drive
two gate-drain connected transistors
·
For the first experiment use the
NMOS current mirror to drive two PMOS gate-drain connected devices.
·
Use the voltages on the
gate-drain connection of the two devices to bias a cascode current
mirror (characterize this mirror as before)
·
For the second experiment switch,
that is, use the PMOS current mirror to drive two NMOS gate-drain connected
devices.
·
Again, use these two voltages to
bias an NMOS cascode current mirror then characterize.
Below in figure 7 is the schematic and simulated results for the NMOS and
PMOS cascode currents using the bias voltages generated from the beta
multiplier.
Figure7
From the simulation results I can see the current should be farily close
even with this cascode structure.
Meaning we have the potential for a much higher output resistance which
means more gain!
Below in table 3 is the consolidated experimental information gathered
from the schematic tested above in figure 7.
|
VDD (V) |
NMOS Cascode Id (uA) |
PMOS Cascode Is (uA) |
|
1 |
< 0.1 |
< 0.1 |
|
2 |
0.34 |
0.35 |
|
3 |
0.47 |
0.45 |
|
4 |
0.58 |
0.54 |
|
5 |
0.66 |
0.61 |
|
6 |
0.74 |
0.69 |
|
7 |
0.80 |
0.78 |
|
8 |
0.86 |
0.85 |
|
9 |
0.92 |
0.93 |
|
10 |
0.98 |
1.01 |
Table 3
From the table the currents seem to increase at a steady rate rather then
reach a steady state value after 2V VDD.
Comparing to the single device in experiment two I was expecting
something similar in this experiment where the current would jump up to some
value and remain close to that value as VDD continued to increase, I am unsure
why this didn’t happen during this experiment.
Conclusion:
This lab provided me with experience in designing and building a beta
multiplier to generate bias voltages.
These bias voltages will be used to set the current in devices to a
known value. The cascode structure in
experiment 3 demonstrated how to get a high output resistance while maintaining
the desired current flow. This amount of
current flow can be used to determine the slew rate when driving a capacitive
load.
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