Lab 6 - EE 420L: Engineering Electronics II
Experiment 1
Below in figure 1 is the schematics for NMOS and PMOS
source followers amplifiers (also known as common-drain amplifiers).
Figure 1
In your lab report discuss the operation of these circuits.
The gate of the transistors are the input terminals and the
source serves as the output terminal with the drain common to both the input
and the output, thus the amplifier is known as the "common
drain". The benefit of using the source follower topology
amplifier is that the input resistance can be adjusted by the R1 and
R3 values in figure 1. These
particular values give an input resistance of 33k Ohms. Also this topology
offers low output resistance. In this
particular schematic the output resistance is calculated by taking the R2
in parallel with 1/gmn. This
gives an output resistance of 55 Ohms for the NMOS and 94 Ohms for the
PMOS. An amplifier with a voltage input
ideally has both an infinite input impedance resulting in zero input
current and a low output impedance. The resistor R2 at node VOUT creates
a potential, VSB , between the source and body
if the body is tied to ground. VSB results in body effect and a
resultant increase in VTH.
The voltage divider in front of the gate is used to set the
bias voltage and the input resistance.
The resistor at the source R2 is used to determine the gate
to source voltage so the device is operating in the saturation region. A
capacitor is used on the input for decoupling so the bias voltage is not
impacted by and DC voltage from Vin.
Simulate the operation of these amplifiers. Hand calculate,
and then verify your hand calculations with experimentation
and simulations, the gains and the input and output
resistances ensuring that your test signals are at a high enough frequency
that the caps have negligible impedance but not so high that the gain is
dropping off. If you build this circuit using electrolytic
capacitors, assuming the input AC signal swings around ground, put the
"+" terminal of the cap on the gate of the MOSFET. Please indicate,
in your lab report, that you understand why the capacitor is connected this
way.
Regarding electrolytic capacitors:
The circuits in the laboratory experiments were all built utilizing
electrolytic capacitors. Electrolytic capacitors are polarized and use a
chemical reaction between the anode and cathode to form an insulating layer. If
the electrolytic capacitor is reverse-biased, the chemical reaction is reversed
and eats away the insulating layer, effectively creating a short between the
terminals. The result is any significant voltage across the capacitor can cause
the capacitor to overheat and explode. Thus, the more negative potential in a
circuit receives the negative terminal of the capacitor.
Theoretical Values
for the Common Drain topology.
Figure 2
Simulation Results
The simulations for the source follower are below in figure
3. From left to right: Initial simulation demonstrating the gain of both
devices is roughly 1; simulation to verify input resistance; simulation to
verify output resistance. The process
for determining the input and output resistance is to create a voltage divider
on the input and output and verify that the gain adjusts as expected. The Spice Error Log was used to determine
the gm values which will be used in all hand calculations,
these values are 18.3mA/V for the NMOS and 10.7mA/V for the PMOS.
Figure 3
As can be seen the gain intially on both devices was roughly
1. If I created a 0.5 voltage divider on
the input and output seperatley I expect the output to decrease by 50%. The middle simulation is the result of
placing a 33k Ohm resistor in series with the input voltage source. As expected the output is half of the
original. This verifys the input
resistance is roughly 33k Ohm. The right
simulation demonstrates the same process on the output where I am creating a
voltage divider on the output and I expect the output to decrease by 50%. As can be seen in figure 3 above this is the
case.
Experimental Results
Below in figure 4 is the combined
experimental results for the NMOS and PMOS in the Common Drain topology with
resistor values from figure 1.
Figure 4
As can be seen when the 33k Ohm resistor is placed in series
with the input source the output is roughly half the original signal. Similarly for the output resistance. I believe the output is rounded due to the
offest voltage and the output is nearing rail voltage. Introducing a higher input signal would
result in a clipped output.
Below in table 1 is the consolidated information collected
above in experiment 1.
|
NMOS |
Theoretical |
Simulation |
Experimental |
|
Gain |
1 |
1 |
1 |
|
Rin |
33k |
33k |
33k |
|
Rout |
55 |
55 |
51 |
|
PMOS |
|
|
|
|
Gain |
1 |
1 |
1 |
|
Rin |
33k |
33k |
33k |
|
Rout |
94 |
94 |
100 |
Table 1
Experiment 2
Below in figure 5 is the topology for common-source
amplifiers.
Figure 5
Discuss the operation of these amplifiers in your lab
report including both DC and AC operation. Hand calculate the
gains and the input/output resistances. How does the source
resistance, Rsn or Rsp, influence the gain.
The common-source(CS) amplifier has the input at the gate and
the output at the drain of the device, thus the input and output have the
source in common. The voltage divider at the gate and the resistors in the
drain and source provide bias voltage and are set to keep the devices operating
in the saturation region. The capacitors are used for decoupling, as in the
source-follower. Unlike the source-follower, the CS is utilized when a larger
gain is desired.
The gain is manipulated via the two resistors, Rsn and Rsp.
These resistor values can be increased or decreased to modulate the current and
thus the voltage at the output. Increasing the value of Rsn or Rsp results
in a decreasing gain, while decreasing the value results in an increasing
gain. This is verified via the theoretical calculations, where Rsn and Rsp are
shown to be inversely proportional to gain.
Theoretical Results
The calculations for the given CS amplifiers are displayed
below in figure 6.
Figure 6
Simulation Results
Below in figure 7 is the combined
simulation results for the NMOS and PMOS in the Common-Source topology from
figure 5.
Figure 7
As can be seen the amplifiers are inverting
the signal and the NMOS has a gain of roughly -7 while the PMOS has a gain of
roughly -6. Again the voltage divider
network was used to verify the input and output resistances from the hand
calculations in figure 6. As can be seen
the outputs for both the input resistance and output resistance values are
roughly 50% of the original. The gain
after the input and output resistance values are implemented are as follows,
for the NMOS the gain is roughly -3.5 and the PMOS gain is roughly -3.
Experimental Results
The consolidated experimental
results are below in figure 8.
Figure 8
The experimental results show that the gain is not quite as
high as the simulation results. The
results of the Rin and Rout experimental values verify
that the hand calculations for the input and output resistance are
correct. As can be seen the output is
roughly 50% of the original amplitude for both input and output resistance
results. This toplogly offers adjustable
input resistance and output resistance by manipulation of resistor values.
Below in table 2 is the consolidated information collected
above for experiment 2.
|
NMOS |
Theoretical |
Simulation |
Experimental |
|
Gain |
-6.9 |
-7 |
-5.7 |
|
Rin |
33k |
33k |
33k |
|
Rout |
1k |
1k |
1k |
|
PMOS |
|
|
|
|
Gain |
-5.4 |
-6 |
-3.5 |
|
Rin |
33k |
33k |
33k |
|
Rout |
1k |
1k |
1k |
Table 2
Experiment 3
Below in figure 9 are the topologies of the common-gate
amplifiers.
Figure 9
Discuss the operation of these amplifiers in your lab
report including both DC and AC operation. Hand calculate the gains
and the input/output resistances. How does the source
resistance, Rsn or Rsp, influence the gain.
The common gate (CG) has the input on the source and the
output on the drain, this results in the gate being common to both the input
and the output. The CG amplifier has low input impedance and high output
impedance. The result is a high voltage gain, but low current gain. This
circuit is DC biased the same way as the source follower and the common-source
amplifiers. The source resistances, Rsn and Rsp , are
still inversely proportional to the gain and thus cause the gain to increase
when they are decreased and cause the gain to decrease when they are increased.
This will be demonstrated in the calculations below.
Theoretical Results
Below in figure 10 is the
theoretical results for the common-gate topology.
Figure 10
Simulation Results
Below in figure 11 is the combined
simulation results for the NMOS and PMOS in the Common-Gate topology from
figure 9.
Figure 11
As can be seen the NMOS has a gain
of roughly 7 while the PMOS has a gain of roughly 5. Again the voltage divider network was used to
verify the input and output resistances from the hand calculations in figure
6. As can be seen the outputs for both
the input resistance and output resistance values are roughly 50% of the
original. The gain after the input and
output resistance values are implemented are as follows, the NMOS gain is
roughly 3.5 and the PMOS gain is now roughly 2.5.
Experimental Results
The consolidated experimental
results are below in figure 12.
Figure 12
The experimental results show that
the gain does not match simulation results or the hand calculations. The results of the Rin and Rout
experimental values verify that the hand calculations for the input and output
resistance are correct. As can be seen the
output is roughly 50% of the original amplitude for both input and output
resistance results. This toplogly offers
adjustable input resistance and output resistance by manipulation of resistor
values.
Below in table 3 is the
consolidated information collected above for experiment 3.
|
NMOS |
Theoretical |
Simulation |
Experimental |
|
Gain |
6.5 |
7 |
12 |
|
Rin |
155 |
155 |
150 |
|
Rout |
1k |
1k |
1k |
|
PMOS |
|
|
|
|
Gain |
5.2 |
5 |
1 |
|
Rin |
193 |
193 |
400 |
|
Rout |
1k |
1k |
1k |
Table 3
Experiment 4
Below in figure 13 is the push-pull amplifier topology.
Figure 13
Discuss the operation of this amplifier in your lab report
including both DC and AC operation. Hand calculate the gain of
this amplifier. Do you expect this amplifier to be good at sourcing/sinking
current? Why or why not? What happens to the gain if the 100k resistor is
replaced with a 510k resistor? Why?
A push-pull amplifier is designed
to have an output that can drive a current in two directions through a load. To
implement a push-pull amplifier, a PMOS and an NMOS are used to source current
through the load and sink current from the load. These amplifiers are used for
low distortion, high efficiency and high output power. Under DC conditions the
devices are gate drain connected which means the devices are always operating
in saturation. The input and output are tied by the 100kΩ resistor
allowing the circuit to be self-biased with no DC current flow in the
transistors. The output is also limited by the rails. A positive input current
causes the gate of M1 to increase until it is cut off while the gate of M2 also
increases and turns on. If the input current is negative, the opposite
occurs. A positive AC input current results in the gates of both
devices increasing and shutting off M1. The circuit contains both a PMOS and
NMOS and depending upon the device that is on at a given time the result is
either sourcing current to the load with the PMOS or sinking current from the
load with the NMOS. Thus, this amplifier is good at sourcing/sinking current.
The amplifier gain is linearly related to the R1 resistor value, as
demonstrated in the theoretical calculations below in fugre 14. Increasing the 100kΩ resistor to 510kΩ
will result in a linear increase in gain.
Theoretical Results
Below in figure 14 is the
theortical results from the figure 13.
Figure 14
Simulation Results
Below in figure 15 is the combined
simulation results for the 100k and 512k push-pull amplifiers from figure 13.
Figure 15
The simulations results were run with .1mV input as the gain of
the push pull amplifier topolgy is multiplied by the resistor value. The simulations show that the gain with a
100k resistor is roughly -2.3k and with the 512k resistor the gain is roughly
-3.5k.
Experimental Results
Below in figure 16 is the consolidated experimental results.
Figure 16
The smallest input voltage from the function generator is
1mV. The 1mv was used as the input when
R1 was 100k and a Voltage divider network was used with values 7k
and 3k to reduce the input by 70% to 0.3mV when R1 was 512k. The experimental results determine that the
gain when R1 is 100k is roughly -2.1k and when R1 is 512k
the gain is roughly -3.2k.
Below in table 4 is the
consolidated information collected above for experiment 4.
|
R1=100k |
Theoretical |
Simulation |
Experimental |
|
Gain |
-2.9k |
-2.3k |
-2.1k |
|
R1=512k |
|
|
|
|
Gain |
-15k |
-3.5k |
-3.2k |
Table 4
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