Lab 5 - EE 420L: Engineering Electronics II
Experiment 1:
Calculate the frequency response of the following circuit.
Ensure you show your clear hand calculations.
The given circuit is below in figure 1 was analyzed to
dertermine the frequency response via nodal analysis at the negative terminal
of the amplifier followed by the calculations displayed in the figure 1.
Figure 1
What can you neglect to simplify the calculation?
To simplify the calculation, R2 is neglected as shown in the
calculations above. Essentially, R1/R2 is much smaller than 1 and thus has a
negligible impact on the circuit, thus R2 can be neglected.
Does the circuit work if you remove the 100k? Why or why not?
The circuit will still work if the 100k resistor is removed
if the op-amp behaves ideally, however this is not likely. The likely result is
the op-amp will have an offset voltage and the 100k resistor is needed to
compensate for the offset. If the 100k resistor is removed and there is a DC
offset at the input terminals, the output will saturate or go to ground
depending on the polarity of the offset voltage.
Does the 100k have much of an effect on the frequency response?
The 100k resistor does not have much of an effect on the
frequency response as verified in the hand calculations above. A more intuitive
explanation is the capacitor is aessentially a short for the current to
flow through during A/C operation. Thus, the 100k resistor has a negligible
impact on the frequency response.
Verify your calculations with experimental results. Show, at
the unity-gain frequency of the integrator, that the input and the output have
the same peak values. Is the phase shift between the input and
the output what you expect? Why or why not?
The following experiments were done using the schematic shown
above in figure 1. I performed half-decade
sweep starting at 10Hz to 5kHz with an input peak to peak voltage of 700mV to
see the operations of the circuit. I
adjusted the starting frequency to 26Hz to better show the results, as there
was too much gain at 10Hz. Below in
figure 2 is the 26Hz, 50Hz and 100Hz operation.
Figure 2
As can be seen the gain at 26Hz is well over 5, and the
signal is clipping. As frequency
increases gain decreases. *NOTE* the
phase shift is acting as predicted in our hand calculations, there is a
positive 90 degree phase shift on the output through each frequency.
Below in figure 3 is the 500Hz, 1kHz, and 5kHz circuit
operation.
Figure 3
As can be seen the trend continues, as frequency increases
gain continues to decrease. *NOTE* the phase shift is still positive 90 degrees
as calculated. Also the gain is dropping
off at 20db per decade as expected. My
input wave function was a sine wave, the integration of sin is cos, and this is
the case for my experimental results.
Below in figure 4 is the output at the calculated unity
frequency demonstrating that the gain is indeed 1.
Figure 4
Below in figure 5 is the operation of the circuit from figure
1 without the 100k Ohm resistor in parralel with the capacitor.
Figure 5
As can be seen there is a DC offset voltage, i.e the voltage
on the + and – terminals of the opamp are not the same. The output is clipping on the + rail. The circuit still works but the 100k Ohm
resister was acting to marginilize the DC offset between the two terminals.
Experiment 2:
Next, design, simulate, and build a square-wave to triangle
wave generation circuit. Assume the input/output frequency is 10 kHz and
the output ramp must swing from 1 to 4 V centered around 2.5 V. Show all calculations and discuss the trade-offs (capacitor and
resistor values, input peak, min, and average, etc.)
Using the hand calculations from
figure 6 below I determined 2 different values for R1 and C1 to see how the
operation compared. I set C1 to be 2.2nF
and .1uF to determine the value for R1.
Figure 6
Below in figure 7 is the spice
simulation results follow by experimental results. *NOTE* the spice simulation
is using an ideal op-amp to determine the results where my experiment was done
with the LM324N.
Figure 7
As can be seen the experimental results do not match the
simulation. The gain of the op-amp using
the 100k Ohm resistor in parralel with the capacitor is to high and is
saturating the op-amp output too quickly.
Below in figure 8 is the spice simulation and results using
the 2.2nF capacitor and 18.9k Ohm resistor.
Figure 8
This result is more along the lines of what I am looking
for. Increasing R3 decreases the gain of
the op-amp.
Below in figure 9 is the experimental results using a 17.8k
Ohm resistor for R3 and a 19.8k Ohm resistor for R3.
Figure 9
The result above demonstrates that a lower gain increased the
time sufficently enough for the output of the op-amp to not saturate before the
input voltage changed. The spikes are
occuring because of the sudden change in voltage from the input, and the
capacitor needs time to react to the change.
I believe it takes 5 time constants for the circuit to react and begin
to act as an integrator.
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