Lab 9 - EE 420L
Authored
by Tyler Ferreira,
ferret1@unlv.nevada.edu
April 5, 2017
Pre-lab work
- This lab will use the level=1 MOSFET model created in lab 8 and, again, the MOSFETs in the CD4007.pdf CMOS transistor array.
- Design and simulate the operation of a BMR that biases the NMOS devices so that they have a gm of 20 uA/V
- Use a simple (big) resistor to VDD for the start-up circuit (explain how the addition of a resistor ensures start-up).
- When
the BMR is operating the current in the big resistor should be much
smaller than the current flowing in each branch of the BMR
- Write-up,
similar to a homework assignment, your design calculations and
simulation results. (This will count as the pre-lab quiz.)
- Ensure that you show the following in what you turn in:
- Hand calculations
- Operation as VDD is swept from 0 to 10 V
- Vbiasn
should stabilize (be constant) after VDD hits a minimum value (estimate
this value of VDD assuming VGS/VSG is a threshold voltage and
VDS,sat/VSD,sat is zero).
- Vbiasp should follow VDD after VDD hits a minimum value (show this in simulations)
- Unstable operation if too much capacitance is shunting the BMR's resistor (see bottom of page 630)
- Comments comparing the hand calculations with the simulation results
Hand Calculations:
MOSFET Models:
LTspice
| Schematic | Bias Voltages | Current |
| 
| 
|
In my hand calculations I calculated a current of 14.6 nA but in my sim the current is rising with the power supply voltage.
I
also found that the threshold voltage for when Vbiasn stabilizes and
Vbiasp follows VDD is at 1.36V but in the simulation it is at 1V.
Experiment 1: Build my BMR design and characterize it as I didn in the pre-lab.
In the lab I had to replace the 100MEG resistor with a 30MEG resistor since that is the largest resistor we had available to us.
I
was able to build my BMR using 4 CD4007 chips. I used 2 chips for the 4
NMOS devices in parallel, 1 chip for the 2 PMOS devices, and 1 chip for
the remaining NMOS device.
My simulated values from LTspice:
The table I generated by changing the power supply voltage and recording the values as seen on the multimeter.
| VDD | Vbiasn | Vbiasp | ID (uA) |
| 0 | 0.00 | 0.00 | 0.00 |
| 1 | 0.02 | 0.08 | 1.00 |
| 2 | 1.00 | 0.20 | 1.20 |
| 3 | 1.80 | 1.80 | 1.50 |
| 4 | 1.80 | 2.20 | 2.00 |
| 5 | 1.80 | 3.80 | 2.30 |
| 6 | 1.80 | 4.20 | 2.50 |
| 7 | 1.80 | 5.80 | 2.60 |
| 8 | 1.80 | 6.20 | 2.90 |
| 9 | 1.80 | 7.80 | 3.00 |
| 10 | 1.80 | 8.20 | 3.20 |
Excel plots of the above values to compare to my simulated results:
The
experimental results of my Vbiasn are a off from my simulated values
but my Vbiasp are almost spot on. My experimental current is almost
double my simulated current.
An error in my experimental values could be from mismatched transistors or incorrect wiring.
Experiment 2: Use my BMR to bias, and thus create, an NMOS current mirror and PMOS current mirror.
Schematics of my current mirrors:
| NMOS Current Mirror | PMOS Current Mirror |
 |  |
Simulations showing how the current varies as the supply voltage varies:
| NMOS Current Mirror | PMOS Current Mirror |
 |  |
The table I generated by changing the power supply voltage and recording the values as seen on the multimeter.
| VDD | NMOS ID (uA) | PMOS ID (uA) |
| 0 | 0.0 | 0.0 |
| 1 | 0.1 | 0.1 |
| 2 | 1.7 | 0.4 |
| 3 | 2.5 | 0.5 |
| 4 | 3.0 | 0.7 |
| 5 | 3.5 | 0.8 |
| 6 | 4.1 | 1.0 |
| 7 | 4.8 | 1.2 |
| 8 | 5.5 | 1.4 |
| 9 | 6.4 | 1.7 |
| 10 | 7.1 | 2.0 |
Excel plots of the above values to compare to my simulated results:
My
experimental current through the NMOS current mirror is off by a lot
compared to my sim. The PMOS current is close to my simulated values.
An error in my experimental values could be from mismatched transistors or incorrect wiring.
Experiment 3: Using
the current mirrors drive two gate-drain connected transistors and use
the generated voltages to bias a cascoded current mirror.
NMOS Cascode Current Mirror:
LTspice Simulation:
The currents Id(M8) and Is(M5) are right on top of each other.
The table I generated by changing the power supply voltage and recording the values as seen on the multimeter.
| VDD | ID (uA) |
| 0 | 0.0 |
| 1 | 0.0 |
| 2 | 0.0 |
| 3 | 0.0 |
| 4 | 0.7 |
| 5 | 1.1 |
| 6 | 1.4 |
| 7 | 1.5 |
| 8 | 1.7 |
| 9 | 2.1 |
| 10 | 2.3 |
Excel plot of the above values to compare to my simulated results:
My experimental current is similar to my simulated current.
PMOS Cascode Current Mirror:
LTspice Simulation:
The currents Is(M7) and Is(M9) are right on top of each other.
The table I generated by changing the power supply voltage and recording the values as seen on the multimeter.
| VDD | ID (uA) |
| 0 | 0.0 |
| 1 | 0.0 |
| 2 | 0.0 |
| 3 | 0.0 |
| 4 | 5.5 |
| 5 | 7.1 |
| 6 | 8.1 |
| 7 | 10.1 |
| 8 | 12.1 |
| 9 | 14.0 |
| 10 | 15.8 |
Excel plot of the above values to compare to my simulated results:
My
experimental results are off from my simulated current. This could be
due to a mismatch of transistors or an error in my wiring.
I will backup my work on to my OneDrive and my desktop:
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