Lab 8 - EE 420L 

Authored by Tyler Ferreira,

ferret1@unlv.nevada.edu

April 5, 2017

Pre-lab work

• Review the datasheet for the CD4007.pdf CMOS transistor array.
• Ensure that you understand how the bodies of the NMOS are tied to pin 7 (VSS, generally the lowest potential in the circuit, say ground) and that the bodies of the PMOS are tied to pin 14 (VDD, generally the highest potential in the circuit, say + 5V). 

In this lab you will characterize the transistors in the CD4007 and generate SPICE Level=1 models. Assume that the MOSFETs will be used in the design of circuits powered by a single +5 V power supply. In other words, don't characterize the devices at higher than +5 V voltages or lower than ground potential.

• Experimentally generate, for the NMOS device, plots of: 

1. ID v. VGS (0 < VGS < 3 V) with VDS = 3 V 
2. ID v. VDS (0 < VDS < 5 V) for VGS varying from 1 to 5 V in 1 V steps, and 
3. ID v. VGS (0 < VGS < 5 V) with VDS = 5 V for VSB varying from 0 to 3 V in 1 V steps. 

• Note that for this last one, if VSS (NMOS body) is ground (again, the Body, VB, is grounded) then the source voltage will be varied from 0 to 3 V in 1 V steps to realize VSB ( = VS - VB = VS) varying from 0 to 3 V in 1 V steps. At the same time VGS will be varied from 0 to 3 V (when VS = 0), 1 to 4 V (when VS = 1 V), 2 to 5 V (when VS = 2 V), and 3 to 5 V (when VS = 3 V). In other words, as VS is increased by 1 V the VGS has to shift up by 1 V as well.
• Assuming that the length of the NMOS is 5 um and its width is 500 um calculate the oxide thickness if Cox (= C'ox*W*L) = 5 pF.
• From this measured data create a Level = 1 MOSFET model with (only) parameters: VTO, GAMMA, KP, LAMBDA, and TOX.
• Compare the experimentally measured data above (the 3 plots) to LTspice-generated data (again, 3 plots) and adjust your model accordingly to get better matching.
• Experimentally, similar to what is seen on the datasheet (AC test circuits seen on page 3 of the datasheet), measure the delay of an inverter using these devices (remember the loading of the scope probe is around 15 pF and there is other stray capacitance, say another 10 pF).
• Using your model simulate the delay of the inverter and compare to measured results. Adjust your SPICE model to get better matching between the experimental data and the measured data.
• Repeat the above steps for the PMOS device where VDS, VGS, and VSB are replaced with VSD, VSG, and VBS respectively.

Experiment 1: Characterization of NMOS device

Handwork:

Important Values:

My Level = 1 MOSFET model: 

ID v. VGS (0 < VGS < 3V) with VDS = 3V

Scope Image	LTspice Sim

   
ID v. VDS (0 < VDS < 5 V) for VGS varying from 1 to 5 V in 1 V steps

 
Experimental Results:

VGS = 1V
VGS = 2V
VGS = 3V
VGS = 4V
VGS = 5V

   
LTspice Simulation:

    
ID v. VGS (0 < VGS < 5 V) with VDS = 5 V for VSB varying from 0 to 3 V in 1 V steps

 
Experimental Results:

VSB = 0V
VSB = 1V
VSB = 2V
VSB = 3V

 
LTspice Simulation:

 
Experiment 2: Characterization of PMOS device
 
Handwork:

 
Important Values:

   
My Level = 1 MOSFET model:

 
ID v. VSG (0 < VSG < 3V) with VSD = 3V

   

Scope Image	LTspice Sim

 
ID v. VSD (0 < VSD < 5 V) for VSG varying from 1 to 5 V in 1 V steps

 
Experimental Results:

VSG = 1V
VSG = 2V
VSG = 3V
VSG = 4V
VSG = 5V

   
LTspice Simulation:

   
ID v. VSG (0 < VSG < 5 V) with VSD = 5 V for VBS varying from 0 to 3 V in 1 V steps

   
Experimental Results:

VSB = 0V
VSB = 1V
VSB = 2V
VSB = 3V

     
LTspice Simulation:

   
Experiment 3: Simulate the delay of the inverter
 
I will connect my CD4007 chip following the data sheet:

 
Schematic:

 

Scope Image	LTspice Sim

I will backup my work on to my OneDrive and my desktop:

 
 
 
 
 
 
 
 
 
 
 
 
 

Return to the directory listing of my labs

Return to the directory listing of students in EE 420L, Spring 2017

Return to the EE 420L, Spring 2017 webpage