ECE 421L - Lab 6

John Huang

Huangj19@unlv.nevada.edu

Spring 2015

   

Lab Description:

Lab 6 is to learn about single-stage transistor amplifiers. We will be looking at 4 different types of single stage amplifiers.

The source follower (common-drain), common-source, common-gate and push-pull amplifier.

All experiments were run at 10kHz to ensure that our capacitor have negligible impedance.

All experiments that required capcactiors were done using electrolitic capacitors with the positive terminal connected to the higher potential and the negative potential connected to the lower potential.

This means that the positive side is usually connected to the gate of the mosfet while the negative side is connected to the function generation (vin).

 

This lab will utilize the ZVN3306A and ZVP3306A mosfets.

 

Below is the schematic for our NMOS and PMOS source follower/common-drain amplifier.

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/1.JPG

We can tell that this design is a common-drain amplifier because both the inputs are coming into the gate of the mosfet and out the source of the mosfet.

The remaining terminal is the drain which makes it a common-drain amplifier.

 

DC simulation:

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/2.JPG

 

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/3.JPG

 

DC hand calculations:

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/4.JPG

 

AC simulation:

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/5.JPG

 

We can see that the gain for the NMOS and PMOS is 1 since Vin is set at 100mV.

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/6.JPG

  

AC hand calculations:

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/7.JPG

 

Experiment:

NMOSPMOS
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/8.JPGhttp://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/9.JPG

We can see that the gain of both NMOS and PMOS are approximately 0.9-1.

 

If we use an AC analysis we can again verify the gain of the source follower.

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/10.JPG

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/11.JPG

And from our simulations this proves to be almost true being that the gain of the NMOS is 0.947 and PMOS is 0.910.

 

Input resistance:

We know that the 50k resistor and the 100k resistor is in parallel, therefore the input resistance would be 33k.

In order to measure this value, we added our own 33k resistor in series to this input resistance.

This would effectly divide our input voltage by half, giving us half our output voltage.

Knowing that this gives us half out output voltage we can then conclude that the input resistance is very close to our calculated input resistance.

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/12.JPG

 

NMOSPMOS
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/13.JPGhttp://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/14.JPG
You can see that the output voltage is half of the input voltage for both the NMOS and PMOS.

Simulation to show what's to be expected by placing resistor with the input resistance.

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/15.JPG

 

Output resistance:

We know that our output resistance is 1k in parallel with 1/gm.

In order to measure this value, we add a resistor with the same value (55 for NMOS and 94 for PMOS) in series with a large capacitor and connect it parallel to the 1k resistor.

We use a large capacitor in this case so that we can avoid messing up the biasing. 

Knowing that this gives us half out output voltage we can then conclude that the output resistance is very close to our calculated output resistance.

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/16.JPG

 

NMOSPMOS
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/17.JPGhttp://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/18.JPG
You can see the the output voltage is about half the voltage of the input voltage for both the NMOS and PMOS.
Once again we can see that the simulation shows half of our original gain when adding the resistor to the output.
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/19.JPG

 

Below is the schematic for the common-source amplifier.

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/20.JPG

The common-source amplifier is similiar to the common-drain, the input is coming into the gate of the mosfet however the output is going out the drain compared to the source of the common-drain amplifier.

Thus making the common node the source terminal of the mosfet.

 

DC simulation:

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/21.JPG

 

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/22.JPG

 

DC hand calculations:

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/23.JPG

 

AC simulation:

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/24.JPG

 

Since Vin is 10mV, we can see that the NMOS has a gain of -7 while the PMOS has a gain of -5.

You can see that the gain is negative since the graph is out of phase.

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/25.JPG

  

AC hand calculations:

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/26.JPG

The source resistance, Rsn or Rsp, will cause the gain to decrease if the source resistance is increased.

 

Experiment:

NMOSPMOS
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/27.JPGhttp://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/28.JPG
We can see that the gain of the NMOS is 5.75, while the PMOS only has a gain of 1.7.
This discrepancy can be caused because of how our value of gm is based off our models text file when the actual gm can be different.
 
Another AC analysis will show the gain of the common-source amplifier.
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/29.JPG
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/30.JPG
From our simulation we can see that the gain of the NMOS was 6.8 while the PMOS was 5.3, which is some-what close to our experimental results.
 
Input resistance:
Applying the same methodology of measuring input resistance from the common-drain.
Using the 33k resistor at the input of Vin. We will get half the output for NMOS and PMOS.
Knowing that this gives us half out output voltage we can then conclude that the input resistance is very close to our calculated input resistance.
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/31.JPG
 
NMOSPMOS
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/32.JPGhttp://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/33.JPG
Again we have half the input voltage for the output voltage after adding the resistor.
Simulation showing the gain after adding the resistor is half of the original gain.
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/34.JPG
 
Output resistance:
Applying the same methodology for measuring output resistance from the common-drain.
We used a 1k resistor for both the NMOS and PMOS and connected them in parallel to the 1k resistor in the output voltage.
Knowing that this gives us half out output voltage we can then conclude that the output resistance is very close to our calculated output resistance.
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/35.JPG
 
NMOSPMOS
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/36.JPGhttp://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/37.JPG
For the output resistance we again get half of the input voltage for the output voltage when placing the resistor in parallel with the 1k.
Simulation to show the gain is half of the original after adding the resistor.
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/38.JPG

 

Below is the schematic for the common-gate amplifier.

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/39.JPG

The common-gate amplifier just like the other two has it's input at the source terminal and it's output at the drain terminal, leaving the gate to be the common node.

 

DC simulation:

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/40.JPG

 

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/41.JPG

 

DC hand calculations:

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/42.JPG

 

AC simulation:

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/43.JPG

 

Since Vin is 10mV, we can see that the NMOS has a gain of -7 while the PMOS has a gain of -5.

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/44.JPG

  

AC hand calculations:

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/45.JPG

The source resistance, Rsn or Rsp, will cause the gain to decrease if the source resistance is increased.

 

Experiment:

NMOSPMOS
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/46.JPGhttp://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/47.JPG
We can see that the gain of the NMOS is only 4.9, while the PMOS is only 2.6.
Again we can assume that the gm values we used in our hand calculations differ from those in the op-amps and in the simulation models text.
AC simulation to show the gain being a bit closer to our hand calculated gain.
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/48.JPG
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/49.JPG
 
Input resistance:
Applying the same methodology of measuring input resistance from the common-drain.
Using the 33k resistor at the input of Vin. We will get half the output for NMOS and PMOS.
Knowing that this gives us half out output voltage we can then conclude that the input resistance is very close to our calculated input resistance.
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/50.JPG
 
NMOSPMOS
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/51.JPGhttp://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/52.JPG
Once again we can see that based on the value of the resistor we placed with the input resistance would give us half of the input voltage.
This is true for both the NMOS and PMOS.
Our simulation once again shows how adding this resistor will make the output half of the original gain.
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/53.JPG
 
Output resistance:
Applying the same methodology for measuring output resistance from the common-drain.
We used a 1k resistor for both the NMOS and PMOS and connected them in parallel to the 1k resistor in the output voltage.
Knowing that this gives us half out output voltage we can then conclude that the output resistance is very close to our calculated output resistance.
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/54.JPG
 
NMOSPMOS
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/55.JPGhttp://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/56.JPG
Adding the resistor in parallel to the 1k resistor from the output again changes our gain to half of the original value.
From our experimental values, it seems that the PMOS was a bit less than half but its still within the margin of half of the original gain.
Simulation to show how adding the resistor changes our gain by half.
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/57.JPG
 
Below is the schematic of a push-pull amplifier.
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/58.JPG
The push-pull amplifier's output and input is tied by the R1 resistor. This makes the circuit self biased and there is no DC current flowing through the mosfets.
 

DC simulation:

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/59.JPG

 

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/60.JPG

 

DC hand calculations:

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/61.JPG

 

AC hand calculations:

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/71.JPG

 

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/72.JPG

We can see that the gain is directly influenced by the resistance value of R1.

Therefore if we increase the value of resistor our gain would also increase.

Theoretically our gain would be 5 times as much compared to the 100k resistor if we use a 510k resistor.

 

AC simulation:

 

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/62.JPG

R1 = 100k

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/63.JPG

R1=510k

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/64.JPG

We can see that our gain with the 510k resistor starts to saturate and go towards VDD and GND.

 

Using an AC analysis we might be able to get an actual gain value. 

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/68.JPG

 

We calculated a gain of -2.9k however our sim only showa  gain of -1.99k.

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/69.JPG

Trying this using the 510k resistor, we should still get 5 times what we got with the 100k resistor, however this is not the case.

The saturation that happens as the gain gets too large causes the output gain to not be represented acrruately.

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/70.JPG

 

In order to fix this problem we use a voltage divider at the input in order to see the large gain.

Here we are simply just use a simple voltage divider made with a 1k and 9k resistor, making the voltage of vin 0.1 times smaller.

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/65.JPG

 

Here we can see the gain is 10 with the 100k resistor.

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/66.JPG

 

Here we can see the gain is 48 with the 510k resistor which is much more close to a increase of 5 times the gain when comparing the 100k resistor gain.

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/67.JPG

 

Experiment:

Our experiment was done starting with the voltage divider, even though it says channel 1 is 100mV, it is actually only 10mV

We can see that the gain with the 100k resistor is about 50, but with the 510k resistor is 120. 

Even our experiment did not come out as expected with the gain, but we can say that as we increase the resistor value of R1, our gain will also go up.

R1 = 100kR1 = 510k
http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/73.JPGhttp://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/74.JPG

 

Conclusion:

From this lab, we learned the three different single stage amplifiers, common-source, common-drain, common-gate. We learned how to identify one from the other and how to determine the gain of each amplifier.

We learned how to measure the input and output resistance through adding a resistor and determining how the gain is affected.

We also learned how the push-pull amplifier works and how you can change the resistor in order to increase or decrease the gain, however it's uses start to fall off when approaching very high gains or high voltages.

 

Back up:

Make sure you back up your whole CMOSedu folder with all your labs by compressing the folder and sending it to yourself through email.

http://cmosedu.com/jbaker/courses/ee420L/s15/students/huangj19/lab6/75.JPG

 

 

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