Lab
9 - EE 420L - Design of a Beta-Multiplier Reference (BMR) using
the CD4007 CMOS Transistor Array
Pre-lab work
- Review
the lab write-up.
- Review
the datasheet for the CD4007.pdf CMOS
transistor array.
- Design, simulate, and test a BMR with the
models made from last lab.
Introduction
This
lab required us to use the previously
characterized transistors (CMOS pairs) in the CD40007 CMOS
array from lab 8.
By measuring our drain current vs a sweeping VGS/VSG or VDS/VSD a few
times along with measuring body effect as we alter VSB/VBS, we can
collect enough data to create a level 1 model in LTSpice (VTO, GAMMA,
KP, TOX) for these transistors. We will use this information to create
a beta multiplier reference (BMR).
BMR using
Vbiasp with a PMOS to drive a cascode NMOS current mirror
This experiment
required us to generate bias voltages from the BMR and use one of them
at a time to drive a single MOSFET current mirror. At first, we applied
Vbiasp to the gate of a PMOS and used that as a current source to
activate an NMOS cascode current mirror. The Vbias3 and Vbias4 from the
cascode circuit were applied to the gates of another two cascoded NMOS
transistors to create a third current mirror. All three were measured
with respect to a VDD sweep from 1 to 10 along with all bias voltages.
| VDD sweep 1-10V on BMR with
Vbiasp going to PMOS current mirror driving an N-type CASCODE CM |
| VDD (V) |
Vbiasn
(V) |
Vbiasp
(V) |
Vbias3
(V) |
Vbias4
(V) |
Iref
(A) |
Imirror
(A) |
ICASmirror
(A) |
| 0.998 |
0.069 |
0.0299 |
0 |
0 |
6.000E-08 |
0.000E+00 |
8.300E-08 |
| 1.998 |
0.138 |
0.585 |
1.981 |
0.597 |
1.310E-06 |
2.000E-07 |
2.040E-07 |
| 2.997 |
0.987 |
1.567 |
2.567 |
0.916 |
1.645E-06 |
1.000E-06 |
1.018E-06 |
| 3.996 |
1.011 |
2.555 |
2.556 |
0.944 |
1.905E-06 |
1.000E-06 |
1.464E-06 |
| 4.996 |
1.03 |
3.546 |
2.814 |
0.965 |
2.160E-06 |
1.300E-06 |
1.905E-06 |
| 5.996 |
1.048 |
4.538 |
2.867 |
0.983 |
2.405E-06 |
1.800E-06 |
2.404E-06 |
| 6.995 |
1.065 |
5.53 |
2.914 |
0.999 |
2.650E-06 |
2.200E-06 |
2.941E-06 |
| 7.994 |
1.081 |
6.525 |
2.957 |
1.014 |
2.895E-06 |
2.900E-06 |
3.545E-06 |
| 8.993 |
1.096 |
7.518 |
2.998 |
1.029 |
3.135E-06 |
3.200E-06 |
9.250E-05 |
| 9.993 |
1.112 |
8.512 |
3.038 |
1.043 |
3.385E-06 |
3.900E-06 |
1.090E-04 |
| VDD sweep 1-10V on BMR with
Vbiasn going to NMOS current mirror driving an P-type CASCODE CM |
| VDD |
Vbiasn |
Vbiasp |
Vbias3 |
Vbias4 |
Iref |
Imirror |
ICASmirror |
| 0.998 |
0.069 |
0.0299 |
0 |
0 |
6.000E-08 |
0.000E+00 |
8.300E-08 |
| 1.998 |
0.138 |
0.585 |
1.981 |
0.597 |
1.310E-06 |
2.000E-07 |
2.040E-07 |
| 2.997 |
0.987 |
1.567 |
2.567 |
0.916 |
1.645E-06 |
1.000E-06 |
1.018E-06 |
| 3.996 |
1.011 |
2.555 |
2.556 |
0.944 |
1.905E-06 |
1.000E-06 |
1.464E-06 |
| 4.996 |
1.03 |
3.546 |
2.814 |
0.965 |
2.160E-06 |
1.300E-06 |
1.905E-06 |
| 5.996 |
1.048 |
4.538 |
2.867 |
0.983 |
2.405E-06 |
1.800E-06 |
2.404E-06 |
| 6.995 |
1.065 |
5.53 |
2.914 |
0.999 |
2.650E-06 |
2.200E-06 |
2.941E-06 |
| 7.994 |
1.081 |
6.525 |
2.957 |
1.014 |
2.895E-06 |
2.900E-06 |
3.545E-06 |
| 8.993 |
1.096 |
7.518 |
2.998 |
1.029 |
3.135E-06 |
3.200E-06 |
9.250E-05 |
| 9.993 |
1.112 |
8.512 |
3.038 |
1.043 |
3.385E-06 |
3.900E-06 |
1.090E-04 |
Conclusion
Our currents did not match
our hand calculations exactly, however we were close within 10times. We
can only hope to accomplish so much since it is difficult to match
transistors if they are all not from the same dye. This was a good
experiment to actually see bias voltages at work and to see how the BMR
can generate a voltage independent of the power supply VDD.
LTspice
model:
.MODEL
N_level1 NMOS LEVEL = 1
+ TOX = 1.13E-14
+ VTO = 0.8
+ GAMMA = 1
+ KP = 9.38E-6
*
.MODEL P_level1 PMOS LEVEL = 1
+ TOX = 1.13E-14
+ VTO = 0.8
+ GAMMA = 1
+ KP = 4.8E-6
Return
Return to EE420L Student
Directory
Return to EE420L
Page
Return to CMOSedu
