Lab

Lab 8 - EE 420L

Authored by Worku, Yetneberk

Today's date 04/29/14

Pre-lab work

1. Review the datasheet of the CD4007 CMOS transistor array.

2. Understand, how the bodies of the NMOS are tied to pin7 (VSS, generally the lowest potential in the circuit, say ground) and the bodies of the PMOS are tied to pin 14 (VDD, generally the highest potential in the circuit, say +5V).

Lab description

A. Lab 8 will characterize the transistors in the CD4007 and generate Level1=1 SPICE models. In other words, don't characterize the devices at higher than +5V or lower than ground potential.

B. Experimentally generate both NMOS and PMOS device , then plots of

ID v. VGS (0 < VGS < 3 V) with VDS = 3 V
ID v. VDS (0 < VDS < 5 V) for VGS varying from 1 to 5 V in 1 V steps, and
ID v. VGS (0 < VGS < 5 V) with VDS = 5 V for VSB varying from 0 to 3 V in 1 V steps.

C. Assuming that the length of the NMOS is 5um and its width is 500 um calculate the oxide thickness if Cox (= C'ox*W*L) = 5 pF
D. From this measured data create a level = 1 MOSFET model with (only) parameters: VTO, GAMMA, KP, and TOX.
E. Use the spice model to generate the above current voltage curves.
F. Finding rising and falling time, also testing propagation delay from low to high, tPLH and from high to low, t PHL.
G. Simulate the delays and compare to the measured results with LTspice model. Adjust the SPICE model to get the better matching between measured data and simulation data

NMOS : Id vs VGS @ VDS =3V