Lab Project 

Authored by Worku, Yetneberk

E-mail: workuy@unlv.nevada.edu

Today's date  04/29/14

Pre-lab work

1. Review the datasheet of the CD4007 CMOS transistor array. 

2. Understand, how the bodies of the NMOS are tied to pin7 (VSS, generally the lowest potential in the circuit, say ground) and the bodies of the PMOS are tied to pin 14 (VDD, generally the highest potential in the circuit, say +5V).

Lab description

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