What,
in simple terms, is the benefit of the KD1S topology?
Since
1-bit quantizers are
used the transistor matching can
be horrible.
Even
the minor effects of the Kpath
comparator’s offsets can be reduced
by
adding a single pre-amp on the output of the integrator. It’s possible
to
attain > 40 dB SNR (> 6-bits) with matching approaching
50 % (e.g.,
one
transistors threshold at 100 mV while another’s at 200 mV). This is
possible
without calibrations or additional overhead. Considerably larger
SNRs
can be achieved at the cost of conversion bandwidth.
While
the KD1S’s tolerance to mismatches will clearly become more
important
as CMOS technology marches toward the sub-10 nm nodes,
other
benefits include: 1) the natural way the KD1S interfaces with
software
for ease of changing the ADC’s characteristics, 2) the higher-
sampling
frequency, 3) it’s small and low power, and 4) the design is
easy
to move between process nodes.