Won’t
timing issues (e.g., **clock skew** and** clock
jitter**) that plague *every* time-interleaved
topology be a
problem with the KD1S topology?

o The
layout size of the KD1S is small and regular. It is possible to design
a clock
distribution tree to minimize clock skew errors.

· Even so,
won’t a few picoseconds of skew be a big deal for a GHz,
high-speed ADC? Yes, however, the standard deviation of the timing skew
due to
a path difference is reduced by both the number of paths, *K _{path}*,
and the oversampling ratio,

o One *big
difference* between KD1S and a time-interleaved ADC
is that the forward
path in the KD1S is shared. It’s not shared in a time-interleaved ADC
topology
and thus the KD1S is much more immune to timing errors.

· If the
timing errors are introduced via the comparators (clock
jitter, clock skew, or comparator metastability) then these
errors are
shaped in the same manner as the quantization noise. They are then
filtered out
with the *K _{path }*–
paths and the digital filtering.
Practically, if the comparators can make a decision and charge the
switched-capacitors within the relatively slow

· Timing
errors introduced via the switched-capacitors used in
the *K _{path}* feedback
paths connected to the op-amp
are lowpass filtered. They experience the modulator’s signal transfer
function,
the inherent filtering due to the switched-capacitor RC charging time,
the
filtering (averaging) due to using

o For a
qualitatively understanding imagine adding, between the
rising edges of an input clock signal, additional phase-shifted clocks (*K _{path}*-1
phases). As

· Because
of the shared forward path, the *K _{path}* feedback
paths, and the use of oversampling (

* To
be precise the errors associated with comparator delay influence the
in-band
noise as discussed in detail here.