Won’t
timing issues (e.g., clock skew and clock
jitter) that plague every time-interleaved
topology be a
problem with the KD1S topology?
o The
layout size of the KD1S is small and regular. It is possible to design
a clock
distribution tree to minimize clock skew errors.
· Even so,
won’t a few picoseconds of skew be a big deal for a GHz,
high-speed ADC? Yes, however, the standard deviation of the timing skew
due to
a path difference is reduced by both the number of paths, Kpath,
and the oversampling ratio, K. For a
5 ps variation, for
example, if Kpath =
8 and K = 8
then the effective oversampling
ratio is 64. The effective
timing skew is then not 5 ps but rather 625 fs
(see Secs.
5.2.1 and 5.2.2 for detailed
discussions). Note that this same discussion, and the benefits of
oversampling,
also applies to problems caused by clock jitter.
Detailed
discussions can be found here.
o One big
difference between KD1S and a time-interleaved ADC
is that the forward
path in the KD1S is shared. It’s not shared in a time-interleaved ADC
topology
and thus the KD1S is much more immune to timing errors.
· If the
timing errors are introduced via the comparators (clock
jitter, clock skew, or comparator metastability) then these
errors are
shaped in the same manner as the quantization noise. They are then
filtered out
with the Kpath –
paths and the digital filtering.
Practically, if the comparators can make a decision and charge the
switched-capacitors within the relatively slow Ts/2
time
interval, then these errors are negligible* and the timing errors
associated
with clocking the switched-capacitors, discussed next, dominate.
· Timing
errors introduced via the switched-capacitors used in
the Kpath feedback
paths connected to the op-amp
are lowpass filtered. They experience the modulator’s signal transfer
function,
the inherent filtering due to the switched-capacitor RC charging time,
the
filtering (averaging) due to using Kpath feedback
paths, and the digital filtering resulting from averaging K
outputs.
As mentioned above the last two reductions cause the variance of the
jitter to
drop by the product of Kpath and K.
This improves (makes more practical) the clock jitter requirements for
a
KD1S-based data converter.
o For a
qualitatively understanding imagine adding, between the
rising edges of an input clock signal, additional phase-shifted clocks (Kpath-1
phases). As Kpath increases
the effective sampling
rate goes up (distance between rising edges decreases) until
the sampling
is effectively continuous-time. The mathematical description
including
global jitter, localized (one path) jitter, and skew may be involved
but the
concept can be understood with this simple description.
· Because
of the shared forward path, the Kpath feedback
paths, and the use of oversampling (K), the KD1S is
a step in the right
direction towards implementing practical high-speed ADCs in nano-CMOS.
* To
be precise the errors associated with comparator delay influence the
in-band
noise as discussed in detail here.