Isn’t the KD1S in Fig. 9.4 simply a multi-bit modulator, Sec. 7.3.4?

No, for several reasons.

· First the ideal SNR for a first-order multi-bit DS modulator is 6.02N + 1.76 – 5.17 + 30logK where K is the oversampling ratio and N is the number of bits used in the multi-bit quantizer (ADC) and DAC. The key thing to note is that the SNR increases linearly with increases in N. For the KD1S modulator the SNR (using 1-bit quantizers and DACs) is 6.02 + 1.76 – 5.17 + 30logK + 30logK_path where K_path is the number of feedback paths (deltas). So, as a comparison, for a clock rate of 100 MHz and a conversion bandwidth, B, of 6.25 MHz, we can write

o For a 3-bit multi-bit DS (seven comparators and eight resistors), f_s = 100 MHz and K = 8 (for B = 6.25 MHz), the SNR = 18.06 + 1.76 – 5.17 + 30log8 = 41.7 dB

o For an 8-path KD1S (eight comparators), f_s = 100 MHz, f_s,new = 800 MHz, K_path = 8, K = 8 (for B = 6.25 MHz), the SNR = 6.02 + 1.76 – 5.17 + 30log64 = 56.8 dB

o The power dissipation is higher for the multi-bit DS

· Second, the gain, G_c, of a 1-bit quantizer (a comparator) can vary from 1 to infinity (actually, the gain of the comparator) as seen in Fig. 7.15 of the book. The gain of a multi-bit quantizer is very limited, Fig. 7.16, and close to 1. This later limitation severely limits the robustness of the resulting feedback system. Perhaps more important than this is that 1-bit quantizers are inherently linear!

· Finally, the sampling rate in the KD1S modulator is K_path times larger than the sampling rate in the ordinary DS modulator resulting in benefits from less aliasing to the ability to use differing digital filters that result in wider conversion bandwidths.

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