In the switched-capacitor
circuits discussed in the MSD book all that sample
an analog signal for the first time also, effectively, pass the
signal through a
Sinc response filter, Eq. (2.16), because of the S/H operation. So,
for example,
if CF = 0
in Fig. 2.35, the output isn’t just a delayed, by a half-clock cycle,
replica of the input [Eq. (2.47) with CF = 0]
but rather a half-clock cycle
delayed S/H version of the input. We purposely don’t include this
response to
keep the equations tractable. Also, for many switched-capacitor
circuits the
frequencies of interest are << fs so the Sinc response has little effect on the
circuits’ operation. But, of
course, we should know it’s there!