related to calculating SNR from
output or measurement results when using MATLAB
specifying a maximum step size in a
transient simulation will likely give varying results (up to 6 dB in SNR). For example using .tran 0
doesnít produce results as good as
using .tran 10p 3.2u 200n 10p In
the later statement the step size is limited to 10 ps. The variation in
step size inherent in SPICE leads to effects like clock jitter, see Secs. 5.2.1 and 5.2.2, and thus amplitude modulation
Fig. 5.22) in the converterís output. The cost of limiting the step
increased simulation time, which can be significant.
ratio of the simulation time, Tstop , to the period
of the input
sinewave should be a whole number. For example, if fin
is 3 MHz (Tin
= 333.33 ns) then a simulation time of 3 us (see .tran
where the first 200 ns of data isnít saved to avoid start-up
results in a whole number of input sinewave cycles fitting in the
time (here Tstop/Tin = 3/0.3333 =
9). When we
take the FFT of the data converterís output the input sinewave fits
into one bin (or 5 bins if a Hann
window is used and
the power spectral density of the signal and quantization noise is
that is, it doesnít leak into adjacent bins.
length of the simulation (the
length saved) sets the bin width of the FFT. For a 3 us simulation time
width is 333 kHz. This means that the FFT is calculated at
f = 0, 333k, 666k, 1MEG, 1.33MEG, etc. The number of signal
should be 20% of the number of noise bins (or smaller) in the bandwidth
interest when calculating the SNR.
Using a short simulation time may result in the FFT only containing the
tone (little to no noise) in the bandwidth of interest and thus
inflate the SNR.
the input sinewave period and
thus the simulation time based on the sampling frequency (period, Ts, again the
ratios, Tstop/Tin and Tin/Ts,
should be whole numbers) can, but not necessarily (e.g. a second-order
noise-shaping modulator) result in coherent sampling (the quantization
added to the signal isnít white, page 175). Drastic changes in the SNR may be observed using this
if the sampling frequency is
176 MHz we might set the input frequency to 2.93333 MHz and the
time as 3.068 us, or .tran 10p
3.268u 200n 10p UIC
and Vin Vin
0 DC 0 SIN 2.5 2 2.933333MEG.
concepts for selecting measurement
time, sampling frequency, and input frequency should follow these
where possible, when testing the data converter. This may be
requiring the oscillator generating the sampling clock be phase-locked
oscillator generating the input to the data converter.
all of these the SPICE-simulated SNR
is still generally limited to < 50 dB (< 8-bits), not
because of SPICE
accuracy, but rather to keep the simulation time reasonable. To improve
SPICE-simulated SNR the tolerances,
need to be reduced (say by a factor of 10). SPICE simulation is still
check connectivity, integrator output swing, and other basic behavior;
the silicon will generally perform better, more in line with theory,
SPICE simulation will indicate.
Saxena, V., "K-Delta-1-Sigma
Modulators for Wideband Analog-to-Digital Conversion.pdf,"
Doctoral Dissertation, Boise State University, April 2010.