I have one question…you designed all of your circuits for nominal process variations. Can we get a
netlist for same 50 nm process for slow and fast corners? Please guide me on how to design a circuit
so that it will give good results in all the corners. Should I plot the table like you plotted in chapter
9 for each process corner? If so then which current should I take to start of my design as it will give
different drain currents, gm, and fT for the same W/L? How should I proceed?
(I think that was more than one question ;-)
Yes, you have to design for nominal since that centers your design. You don't design at the corners
because then the design performance is worse at the opposite corner. Simulations are used to verify
that your design meets specs with process variations. No need for new tables or hand calculations
since, again, you design for nominal conditions and verify, via simulations, that the design meets the
requirements. If the design has issues you look for the problem and attempt to fix it. The models used
in the book are not from any real process but they are representative of real CMOS technology. You
can generate all kinds of different models (slow, fast, etc.) by going to http://ptm.asu.edu/ . You can
If you really want corner models for the 50 nm models from the book the DVT1 in the BSIM4 parameter
can be skewed for a hack. Do not mess with TOX since it's tied to too many other model parameters.
NSH and NSD could be used if you had knowledge about additional IDS variation above and beyond
what you might get from VT shifts. I’d stick with a simplistic DVT1 skew for a hack. A 20 mV sigma
(± 60 mV at 3σ) is a decent starting point for typical performance. 12-15 mV would be the low end of the
die-to-die variation expectations for a 50 nm device.