I have several questions about the voltage regulator presented in Sec. 24.5.

1. Why estimate the location of the f₂ output pole, which will be our dominate pole, using the closed loop output resistance and not the open loop output resistance? 

Since the load capacitance is used to compensate the op-amp we can Thevenize the op-amp and reference voltage so that the result is a single-pole RC circuit with a BW of 1/(2pR_out,CLC_L). The points are increasing C_L stabilizes the regulator while supplying more current, decreasing R_out,CL, makes the regulator more likely to be unstable. 

When we think about loop stability, we think about reducing the total open loop phase lag appearing at the v(-) input. 

Yes, however, you always have a -90 degree phase shift due to a dominant pole. In this case you want this phase shift to be due to the load and not the internal high-impedance node. In other words, you want f₂ (the pole on the output of the op-amp) to be much smaller than f₁ (the pole associated with the output of the diff-amp).

With op-amps, the dominant pole of the system is the 3-dB frequency of the open loop gain (which comes from R₁ and C₁). But here we get that dominant pole frequency using the closed loop resistance. I wish I could justify that.  

You don't want the design to have a dominant pole due to R₁ and C₁ but rather from R₂ and C_L (which is approximately equal to C₂). Note this is what makes this design unique. You have to have a huge load C to supply current to the load for fast transients, to bypass the slower op-amp action, and to compensate the feedback loop. 

Further, once this choice is made, the open loop gain appears in the numerator of the expression for f₂. One can then make the argument that there is a gain versus stability trade, since any increased gain pushes out f₂ (the dominant pole). But I can't justify that claim if I can't explain using the closed loop expression for R₂ in f₂.

Yes, increasing the open-loop gain does push out f₂ which is bad and why we can't have too high open-loop gain (as discussed in the book). If the gain is increased by increasing R₁ then f₁ moves down towards f₂ which is also bad (again, discussed in the book). The bottom line is that you have to have a big decoupling capacitor on the output of the regulator to supply charge for fast current needs so to minimize the power drawn by the regulator you have to compensate with the pole at f₂. Of course, you can still design a regulator to be compensated with f₁ (the pole on the output of the diff-amp) but you will need a very large compensation capacitor and the design will burn more power (and be much, much, larger). 

2. At interviews everyone says that decreasing R_L decreases stability, and I find that as well in my simulations. However, we wouldn’t suspect that by looking at the equation for f₂ (24.71). In that expression we have open loop gain in the numerator and R₂ in the denominator. In that expression, wouldn’t the R₂’s cancel? You do say lower down on the same page that a smaller R₂ reduces stability, but is that statement consistent with (24.71)?

Yes, the R₂s cancel in Eq. (24.71). But if R₂ drops this means M7 is supplying more current and thus g_m2 (which is equal to g_m7) goes up increasing f₂ towards f₁ and reducing stability. 

If smaller R₂ reduces stability why reduce it further with R_L (R_L << R₂)? You seem to be saying: “Ok C_L is impossibly large, but by loading down R₂ with R_L, we can reduce C_L. This is equation (24.75).”

So if we make R_L larger than the open-loop gain of the op-amp grows and f₂ drops resulting in, ideally, no change in the unity-gain frequency of the op-amp, f_un. In other words f_un is still less than f₁ so why would we want to ensure a minimum R_L as indicated by Eq. (25.76)??? 

Well, if you remember Miller's theorem, as the gain of the second stage of the op-amp grows the capacitance on node 1 (the diff-amp's output) grows too, (1 + g_m2R₂)C_c, pushing f₁ down towards f₂ and above the unity-gain frequency. The result is an unstable op-amp and hence why we require a minimum load (so g_m2R₂ isn't too big). Good question.

I can agree with that if the idea is to trade stability for a smaller C_L. To have a smaller C_L we have to add R_L. If we want to get back some of the stability just traded away, we can reduce the gain (reduce g_m1, reduce R₁), which is similar to reducing f_un.

But then you seem to say that adding R_L won’t reduce stability. The reason is that as current increases in M7, the decrease in R₂ is cancelled by the increase in (g_m7)².

My problem with that is that the product R₂(g_m7)² doesn’t appear in the expression for f₂ (it does appear in the expression for f_un). Actually f₂ boils down to f₂ = g_m1R₁g_m2/2πC_L.  So here’s the question: what is the impact of R_L on stability? And what do we get for using R_L? (My answer: smaller C_L and smaller open loop gain for light current loads).

We need the R_Lmax to keep the second stage gain from getting too big so that f₁ stays above the unity gain frequency, f_un, as discussed above. Reducing R_L pushes out f₂ and reduces the open-loop gain resulting in less control of the regulated output voltage. It also moves f₂ towards f₁ making f₂ no longer a "dominant pole" but rather the system moves towards a second-order system with all of the issues with damping and ringing.

The expression for f₂ given in Eq. (24.71) does have both R₂ and g_m2 (= g_m7) in it since A_OLDC = g_m1R₁g_m2R₂.

Yes, R_L keeps the second stage gain down to keep f₁ > f_un (Miller effect discussed above). The larger we can make f₁ the larger we can make f₂ and thus the smaller we can make C_L (though C_L’s size is generally set by the amount of charge needed for some fast event). Of course the trick is to keep the open-loop gain as large as possible so that the output voltage stays regulated.

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