I have several questions about the voltage regulator presented in Sec. 24.5.


1. Why estimate the location of the f2 output pole, which will be our dominate pole, using the closed loop output resistance and not the open loop output resistance? 


Since the load capacitance is used to compensate the op-amp we can Thevenize the op-amp and reference voltage so that the result is a single-pole RC circuit with a BW of 1/(2pRout,CLCL). The points are increasing CL stabilizes the regulator while supplying more current, decreasing Rout,CL, makes the regulator more likely to be unstable. 


When we think about loop stability, we think about reducing the total open loop phase lag appearing at the v(-) input. 


Yes, however, you always have a -90 degree phase shift due to a dominant pole. In this case you want this phase shift to be due to the load and not the internal high-impedance node. In other words, you want f2 (the pole on the output of the op-amp) to be much smaller than f1 (the pole associated with the output of the diff-amp).


With op-amps, the dominant pole of the system is the 3-dB frequency of the open loop gain (which comes from R1 and C1). But here we get that dominant pole frequency using the closed loop resistance. I wish I could justify that.  


You don't want the design to have a dominant pole due to R1 and C1 but rather from R2 and CL (which is approximately equal to C2). Note this is what makes this design unique. You have to have a huge load C to supply current to the load for fast transients, to bypass the slower op-amp action, and to compensate the feedback loop. 


Further, once this choice is made, the open loop gain appears in the numerator of the expression for f2. One can then make the argument that there is a gain versus stability trade, since any increased gain pushes out f2 (the dominant pole). But I can't justify that claim if I can't explain using the closed loop expression for R2 in f2.


Yes, increasing the open-loop gain does push out f2 which is bad and why we can't have too high open-loop gain (as discussed in the book). If the gain is increased by increasing R1 then f1 moves down towards f2 which is also bad (again, discussed in the book). The bottom line is that you have to have a big decoupling capacitor on the output of the regulator to supply charge for fast current needs so to minimize the power drawn by the regulator you have to compensate with the pole at f2. Of course, you can still design a regulator to be compensated with f1 (the pole on the output of the diff-amp) but you will need a very large compensation capacitor and the design will burn more power (and be much, much, larger). 


2. At interviews everyone says that decreasing RL decreases stability, and I find that as well in my simulations. However, we wouldn’t suspect that by looking at the equation for f2 (24.71). In that expression we have open loop gain in the numerator and R2 in the denominator. In that expression, wouldn’t the R2’s cancel? You do say lower down on the same page that a smaller R2 reduces stability, but is that statement consistent with (24.71)?


Yes, the R2s cancel in Eq. (24.71). But if R2 drops this means M7 is supplying more current and thus gm2 (which is equal to gm7) goes up increasing f2 towards f1 and reducing stability. 


If smaller R2 reduces stability why reduce it further with RL (RL << R2)? You seem to be saying: “Ok CL is impossibly large, but by loading down R2 with RL, we can reduce CL. This is equation (24.75).”


So if we make RL larger than the open-loop gain of the op-amp grows and f2 drops resulting in, ideally, no change in the unity-gain frequency of the op-amp, fun. In other words fun is still less than f1 so why would we want to ensure a minimum RL as indicated by Eq. (25.76)??? 


Well, if you remember Miller's theorem, as the gain of the second stage of the op-amp grows the capacitance on node 1 (the diff-amp's output) grows too, (1 + gm2R2)Cc, pushing f1 down towards f2 and above the unity-gain frequency. The result is an unstable op-amp and hence why we require a minimum load (so gm2R2 isn't too big). Good question.


I can agree with that if the idea is to trade stability for a smaller CL. To have a smaller CL we have to add RL. If we want to get back some of the stability just traded away, we can reduce the gain (reduce gm1, reduce R1), which is similar to reducing fun.


But then you seem to say that adding RL won’t reduce stability. The reason is that as current increases in M7, the decrease in R2 is cancelled by the increase in (gm7)2.


My problem with that is that the product R2(gm7)2 doesn’t appear in the expression for f2 (it does appear in the expression for fun). Actually f2 boils down to f2 = gm1R1gm2/2πCL So here’s the question: what is the impact of RL on stability? And what do we get for using RL? (My answer: smaller CL and smaller open loop gain for light current loads).


We need the RLmax to keep the second stage gain from getting too big so that f1 stays above the unity gain frequency, fun, as discussed above. Reducing RL pushes out f2 and reduces the open-loop gain resulting in less control of the regulated output voltage. It also moves f2 towards f1 making f2 no longer a "dominant pole" but rather the system moves towards a second-order system with all of the issues with damping and ringing.


The expression for f2 given in Eq. (24.71) does have both R2 and gm2 (= gm7) in it since AOLDC = gm1R1gm2R2.


Yes, RL keeps the second stage gain down to keep f1 > fun (Miller effect discussed above). The larger we can make f1 the larger we can make f2 and thus the smaller we can make CL (though CL’s size is generally set by the amount of charge needed for some fast event). Of course the trick is to keep the open-loop gain as large as possible so that the output voltage stays regulated.