Is gm
(and thus device fT)
independent of overdrive voltage (Eq. [9.57])
in
nanometer (or long-channel) CMOS?
Both gm and fT
vary greatly with the overdrive voltage. See Eq. (9.55)
(or,
for long-channels, Eq. [9.36]) and
Fig. 9.33.
The
most important aspect of this
dependence is that to increase CMOS
device
speeds (fT)
you need to increase the overdrive voltage. This is
one
of the reasons why we bias with the
BMR (it's easy to set overdrive
voltage
with changes in temperature and
process).
The
confusion comes from claims that
short channel devices' fT
does
not vary with overdrive voltage
because of saturation velocity effects
(as
seen in Eq. (9.57) if vsat
is constant). vsat
isn't constant and does
depend
on both VGS
and VDS
as indicated on page 299 (clearly gm
does
increase
with overdrive as seen in Fig.
9.33). The reasons for the
variations
in vsat
are outside the
scope of the book (e.g. velocity
overshoot).
Biasing
is often a neglected topic when
learning to design CMOS analog ICs.
This
is unfortunate because it is the
MOST IMPORTANT topic in analog IC
design.
When I look at someone else's
design the first things I look at
are
the threshold voltage of the
process and then VGS
so I
can determine
overdrive.
If the VGS
is close to the threshold voltage (so overdrive
is
close to zero) then I know that the
design will be inherently slow (and
operating
in weak inversion).
If
the overdrive voltages vary from
device to device then the design isn't
optimized
for speed (it's that simple).
If I need more speed, in a two stage
op-amp,
I simply decrease the
compensation capacitor (to push the unity gain
frequency,
fun = gm/2πCc,
out to a higher
frequency) and increase the widths
of
the output buffer (keeping the
overdrives constant, with an increase in
current).
This pushes f2
(see Eq. [24.24]) to a
higher frequency (because
of
the increase in gm2
with the increase in device widths) so
that f2
> fun.
Again,
for general design set
overdrives to 5% of VDD. For
high-speed designs
set
overdrive voltages to 10% of VDD or
more.