IC EXTRACTION AND BACKANNOTATION The following tutorial gives an introduction to parasitic extraction and backannotation using Mentor Graphics' IC Station. In order to do the extraction, the layout should have been completed and it should have passed DRC. This parasitic information extracted is used in simulating the circuit with backannotated RC delays in AccuSim II. Layout Versus Schematic (LVS) The first step to be performed in extraction is to check the layout against the schematic. Ictrace LVS is an IC Station tool used in verifying the connectivity of an ICgraph layout against a source (schematic) connectivity. Follow these steps to do a Mask mode LVS: 1. Invoke IC Station from the command prompt. 2. Open the 2-input NAND cell in Edit mode using the palette menu Cell>Open. 3. Select the ICtrace(M) palette menu. 4. Once in the ICtrace(M) menu, select the LVS item to bring up the LVS dialog box. Using the Navigator button, select nand2/sdl. Leave everything else as such. Fig. 1: LVS Mask Dialog Box 5. Using the Report->LVS palette menu item, open the report. A text window will appear displaying the report of the comparison. LVS Report Listing Conventions Discrepancies: Differences between the layout and source circuits are reported as discrepancies. Each discrepancy is identified by a serial discrepancy number in the LVS report. The layout elements involved in each discrepancy appear on the left hand side of the report. The source elements appear on the right hand side of the report. Discrepancies are separated by dashed horizontal lines. Layout and source elements involved in a particular discrepancy can be viewed graphically in ICgraph by specifying the discrepancy number. Example: ------------------------------------------------------------- 5 ** missing net ** /N$716 ------------------------------------------------------------- This is a "missing net" discrepancy. The discrepancy number is 5. Source net N$716 (on the right) is missing in the layout (on the left). LVS Discrepancy Types The various LVS discrepancy types are described below. For each discrepancy type, the report format and the graphic representation are specified. Error Type Report Format Graphic Example Short Circuit: Indicates a short-circuit in the layout. A short-circuit is detected when two sour-ce nets are connected together in the layout. Layout net is shown on left, 2 corresponding source nets are shown at right. Layout net and 2 corresponding source nets are highlighted. 5 Net VDD //VDD /N$87 Source nets //VDD and /N$87 were connected together in the layout to form the single layout net VDD. Open Circuit: Indicates an open-circuit in the layout, detected when 2 layout nets should be connected to correspond to a single net in the source. Two layout nets are indicated on the left. The corresponding source net is indicated at right. Two layout nets and the source net are highlighted. 5 NetN4 /SIG1 N87 Layout nets N4 and N87 should be connected together to correspond to the single source net /SIG1. Missing Connection: Indicates a missing connection (to an instance pin or a pin of a logic gate generated internally by LVS) in a layout or source net. Occurs when a net in circuit A is connected to more pins of a certain type than corresponding net in circuit B, whose same type connections are matched. Layout net & corresponding source net followed by list of missing connections, represented by the respective instance pins. Layout net, corresponding source net and the badly connected instances are highlighted. Connections to internally generated logic gates are represented by the transistors forming the respective pin of the gate. 5 NetN720 /N$790 ------------- ---------- (NAND):INPUT **missing MP1:G connection ** MN1:G Layout net N720 was matched to source net /N$790 but connection to the NAND input formed by gate pins of transistors /MP1 and MN1 is missing in the source net. The indicated transistors are a pair of MP and MN transistors which form one input of the NAND gate. Missing Net: This type of discrepancy indicates a missing net in the layout or source circuit. This happens when all nets in one of the circuits have been matched and there are some unmatched nets left in the other circuit. The unmatched nets are reported as missing. When encountering this discrepancy, check the numbers of nets reported in the "overall comparison results" section of the report. The net is indicated. The net is highlighted. 5 **missing net** /N$716 Source net /N$716 is missing in the layout. Missing Port: This type of discrepancy indicates a missing port in the layout or source circuit. This happens when all ports in one of the circuits have been matched and there are some unmatched ports left in the other circuit. The unmatched ports are reported as missing. The port and its net are indicated. The port is highlighted. 5 **missing port** IN2 on net:/IN2 Source port IN2 on net /IN2 is missing in the layout. Naming Error: A "naming error" discrepancy may be reported for a layout net, instance or port that has a user-given name. It indicates that there is a net, instance or port, respectively, with identical user-given name in the source but the LVS algorithm decided not to match the two elements to each other because they are differently connected. Instead, LVS chose to ignore the names and match the layout element to some other source element, or to match the source element to some other layout element. A "naming error" discrepancy usually indicates wrong name assignment to layout elements. The layout element and its corresponding source element are indicated on the left and right side of the report respectively. A naming error is indicated by a "ne" mark near the right hand side column of the report. The layout and source instances are highlighted. 5 Net RESET ne /N$34 Sample Reports In the above report, there are discrepancies in the number of ports and their names. To highlight the first discrepancy, use the palette menu Scan>Discreps>First. The other violations can be highlighted from the ICtrace(M) menu Scan>Discreps>Next. To unhighlight the discrepancies, execute the palette menu Unshow>All. Once you identify the discrepancy, go back to the SDL menu and correct the violation. In the above LVS, the ports C.H and F.L are reported under "Missing Port Discrepancy" and the "Naming Error" indicates that there is a mismatch in the naming of the ports. To correct the error, all the ports and their associated nets should be removed (select and delete the ports and their associated nets) first and then reroute and add ports again using SDL menu. Perform DRC on the re-laid cell. If DRC is successful, perform LVS from ICtrace(M) menu. 6. Once you have checked your LVS report and everything is OK, close the LVS report window and save the cell using the pull down File>Cell>Save Cell>Current Context. You are now ready to do Mask mode extraction. Parasitic Extraction (PEX) After your layout passes DRC and LVS, you are ready to backannotate parasitics for simulation. ICextract is an IC Station tool that obtains information from an IC layout about parasitic resistance and parasitic capacitance for creating annotated netlists, or for backannotation. At this point, you can only extract for analog simulation (AccuSim II). Hence, lumped extraction is what you will be performing. Lumped extraction will treat each distinct net as one lumped capacitor and/or resistor. Every point on the net will see the full extracted RC delays, therefore. Hence, a transmission line will look the same no matter where you are on that transmission line. Keep this in mind if you expect different results! Follow these steps to do a Mask mode PEX: 1. Invoke IC Station from the command prompt if a session is not running. 2. Open the 2-input NAND cell in Edit mode using the palette menu Cell>Open, if you don't have the cell open. 3. Select the ICextract(M) palette menu. 4. In the ICgraph window, type the command pex to do parasitic extraction. Pex is a function that has been created for you to perform parasitic extraction. In the prompt bar, enter the viewpoint name nand2/sdl and click on OK. 5. When the extraction is complete, you can open a report window to find the RC delays. Do this using the palette menu Report>All Nets. 6. Save the cell and exit the application. Now you are ready to simulate your circuits with the extracted parameters. Post Layout Simulation The final step in the design process is post-layout simulation. In this section you will see if the circuit has the desired timing and drive characteristics that you had hoped for. You were never told what these specs were, so we will simply check to see if you have a reasonable circuit. You should look for delay through your circuit as well as rise and fall times at the inputs and outputs. 1. Remember from the extraction chapter that you backannotated into your cell's sdl viewpoint. Hence, you should start AccuSim using this viewpoint. 2. Next, load your saved setup which has the windows and parameters from your functional simulation run. Use the pull down menu File>Simulation>Restore>Setup to do this. 3. Now load in your saved forces database with the File->Waveform DB->Load menu. 4. Now type run to run the simulation, again. Note if the signals look bad or wrong in any way. They should not look much different that your functional simulation because there is not much added capacitance nor resistance in the layout. As you can see, there is not much different in running post-layout simulations. In the next chapter you will see how to do hierarchical designs using SDL. in those cases, you will probably get more of a variation from the ideal pre-layout and post-layout simulations.