The Analog Chain Layout

Date: 01/06/20

By David Santiago – Email: santid4@unlv.nevada.edu

Last Edited on 01/07/20 at 4:25pm using Word

We will be instantiating some premade layouts and connecting them to form a top hierarchy layout.

Wiring it all up:

NOTE: Do NOT Wire any pin under a capacitor. The LVS will register a pin as unbounded (wont see the pin) if you instantiate below the ablb layer

Place pin Here:

or

Do NOT place it here:

or

Sub/VDD plane:

Click here to see the layout

VSS plane:

Inputs:

Buffer stage:

Final Layout:

Click here to see the final layout

LVS: