Lab 7 - ECE 421L
Authored
by Batya Vishnepolsky, vishnepo@unlv.nevada.edu
11/7/23
Lab
description
in
this lab we learn about the design of a NAND, XOR, and a full adder using those components
Prelab Description
Tutorial five:
Schem:
![](lab7pics/31ringoscillator.png)
Layout:
![](lab7pics/osc_layout.png)
DRC and LVS:
![](lab7pics/osc_drc.png)
![](lab7pics/osc_lvs.png)
Simulation results:
![](lab7pics/oscillatorsim.png)
Lab work:
We went through the 4 bit inverter and 2to1 MUX and simulated them to learn about them:
4-bit inverter:
Schem:
![](lab7pics/4bit_inv.png)
Symb:
![](lab7pics/4bit_inv_symb.png)
Simulation:
![](lab7pics/4bit_inv_schem.png)
![](lab7pics/4bit_inv_sim.png)
2to1 MUX:
Schem:
![](lab7pics/2to1mux_schem.png)
Symb:
![](lab7pics/2to1mux_symb.png)
Simulation acting as a mux:
![](lab7pics/2to1mux_schem_sim.png)
![](lab7pics/2to1mux_sim.png)
Simulation acting as a demux:
![](lab7pics/2to1demux_schem_sim.png)
![](lab7pics/2to1demux_sim.png)
Explanation for MUX behavior:
Mux behavior:
When
the s input of the mux goes high, the z output will take the previous
A’s input. When the s input goes low (or si goes high), then the z
output thats the previous B’s input.
Demux behavior:
When s input is low, B follows the Z input. When s is high, then A follows the z.
Next I was directed to make a bunch of logic components that could handle an 8-bit input.
8-bit inverter:
Schem:
![](lab7pics/8bit_inv_schem.png)
Symb:
![](lab7pics/8bit_inv_symb.png)
Simulation:
![](lab7pics/8bit_inv_schem_sim.png)
![](lab7pics/8bit_inv_sim.png)
8-bit NAND:
Schem:
![](lab7pics/8bit_nand_schem.png)
Symb:
![](lab7pics/8bit_nand_symb.png)
Simulation:
![](lab7pics/8bit_inv_schem_sim.png)
![](lab7pics/8bit_nand_sim.png)
8-bit AND:
Schem:
![](lab7pics/8bit_and_schem.png)
Symb:
![](lab7pics/8bit_and_symb.png)
Simulation:
![](lab7pics/8bit_and_schem_sim.png)
![](lab7pics/8bit_and_sim.png)
8-bit NOR:
Schem:
![](lab7pics/8bit_nor_schem.png)
Symb:
![](lab7pics/8bit_nor_symb.png)
Simulation:
![](lab7pics/8bit_nor_schem_sim.png)
![](lab7pics/8bit_nor_sim.png)
8-bit OR:
Schem:
![](lab7pics/8bit_or_schem.png)
Symb:
![](lab7pics/8bit_or_symb.png)
Simulation:
![](lab7pics/8bit_or_schem_sim.png)
![](lab7pics/8bit_or_sim.png)
8-bit MUX:
Schem:
![](lab7pics/8bit_mux_schem.png)
Symb:
![](lab7pics/8bit_mux_symb.png)
Simulation (MUX behavior):
![](lab7pics/8bit_mux_schem_sim_mux.png)
![](lab7pics/8bit_mux_sim_mux.png)
Simulation (de-MUX behavior):
![](lab7pics/8bit_mux_schem_sim_demux.png)
![](lab7pics/8bit_mux_sim_demux.png)
Next, I created a full adder schematic, symbol, and simulated it.
Schem:
![](lab7pics/adder_schem.png)
Symb:
![](lab7pics/adder_symb.png)
8-bit versions:
Schem:
![](lab7pics/adder8_schem.png)
Symb:
![](lab7pics/adder8_symb.png)
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