Lab 2 - ECE 421L 

Authored by Sean Troop, troop@unlv.nevada.edu

9/6/2023

Prelab: missing

 ---
  

 

 Lab 2: Design of a 10-bit DAC

 

 

 10-bit DAC schematic

 

Figure_1.png

 

 

 The output resistance of the DAC can be determined by combining the resistors in parallel and thevenizing to combine in series
 The output of the bit is equal to VDD/2^n where n is the bit number
 
 

Figure_1.png

 
 Before simming we would expect the output to have a delay equal to 0.7RC or 0.7*(1k)*(10pf) = 70ns
 Figure_1.png
 

 As shown in the sim the delay to reach half the potential is 70 ns

 
 Shown below is the symbol view of my schematic

Figure_4.png



No load driven simulation

Figure_5.png

Resistive load driven simulation
when the load driven is purely resistive there is no time delay, but when there is a capacative load added there is also a time delay in addition to a signal attenuation.

Figure_6.png

Capacitive load driven simulation


Figure_7.png
Capacitive and resistive load simulation

Figure_8.png

return