Lab 5 - ECE 421L 

Authored by Sean Troop, troop@unlv.nevada.edu

10/10/2023

Prelab backup

Figure_1

Figure_1.png

 

 follow Tutorial 3

 
 Tutorial 3 schematic


Figure_2.png

Tutorial 3 layout

 
 Figure_3.png
Tutorial 3 LVS

Figure_4.png

Tutorial 3 sim results

Figure_5.png

 ---
   

  

  Lab 5: Design, layout, and simulation of a CMOS inverter

  

 

Schematics/Layouts/Symbols for 12u/6u inverter
------------------------------------------------------
Schematic


Figure_15.png


Figure_6.png

Layout

Figure_3.png

Symbol

figure_7.png


Small inverter simulation

--------------------------------------

Simulation state

 

 Figure_8.pngFigure_8.png

Simulation results

Figure_9.png

   



Schematics/Layouts/Symbols for 48u/24u inverter

------------------------------------------------------
Schematic

Figure_10.png

Layout
Figure_11.png

Symbol
Figure_12.png

Small inverter simulation

--------------------------------------

Simulation state

Figure_13.png

Simulation results

 Figure_14.png  

======================================

 End of lab 5

  Backup data

 return