Lab 4 - ECE 421L 

Authored by Sean Troop, troop@unlv.nevada.edu

9/27/2023

Prelab backup

Figure_1

Figure_1.png

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  Lab 4:  IV Charcteristics and layout of NMOS and PMOS devices in ON's C5 process

  

 

Generate 4 schematics and simulations


Simulating ID vs. VDS of an NMOS. VGS varies from 0 to 5V. VDS varies 0 to 5v


  Schematic

 

Figure_2.png


    Simulation

 
Figure_3.png
 

    ID Vs. VGS of NMOS. VDS = 100mv. VGS varies from 0 to 2v.

     Schematic
    figure_4.png

    Simulation
     
Figure_5.png
 
     ID vs. VSD of PMOS. VSG varies 0 to 5 V. Vsd Varies 0 to 5 m.
   
 

    Schematic
  figure_6.png    

 

   Simulation

  figure_7.png

 

    ID vs VSG of PMOS. VSD = 100mv VSG varies 0 to 2v. 

 

     Schematic

   
  Figure_8.png

       

      Simluation

   figure_9.png

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Layout of NMOS 

 figure_10.png

 Layout of NMOS + Probe pads

  figure_11.png

   Schematic 

Figure_12.png

  Design passes LVS 

Figure_13.png

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Layout of PMOS

Figure_14.png

 Layout of PMOS + Probe pads

Figure_15.png


    Schematic

  Figure_16.png

   Design passes LVS

Figure_17.png

   

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