Lab

Project - ECE 421L

Authored by Anthony Peytchev,

Email: peytchev@unlv.nevada.edu

11/11/2023

Non-Inverting Buffer Circuit

Task:

Design a non-inverting buffer circuit that presents less than 100 fF input capacitance to

on-chip logic and that can drive up to a 1 pF load with output voltages greater than 7V (an output logic 0 is near ground

and an output logic 1 is greater than 7V). Assume VDD is between 4.5V and 5.5V, a valid input logic 0 is 1V or less, a valid

input logic 1 is 3V or more. Show that your design works with varying load capacitance from 0 to 1pF. Assume the slowest

transition time allowed is 4 ns.

TextBook Reference:

Intuitive Summary of How it Works:

- Input
The clock oscilates from 0 to 1 and early in the circuit there are two inverters that generate complimentary clock signals that are out of phase with eachother so when input is high inv_12 outputs a low signal and vice versa, this makes the output go to gnd when low and go to 2VDD when high. A input of 0 gets inverted into 1(VDD) which then charges the smaller Capacitor C0 to turn on the transistor switch that will charge up C1 with greater capacitance.

- Pump Up and Discharge
The capacitance of the capacitors determine the amount of charge they can hold in this design there are two capacitors one with much less capacitance C0 than the other with more capacitance C1 the one with less capacitance holds less charge as its purpose is to ensure N1 NMOS transistor switch charges reliably and prevents leakage current from potentially turning on the N1 transistor unintentionally. It is also important for the C0 Capacitor to provide enough time for the C1 Capacitor to charge up to VDD and thus having C0's capacitance be too low will limit the charge held in C1 and thus limit the output voltage so it is important for C0 to have enough capacitance so C1 can properly charge up.
The capacitor that is meant to boost the voltage to 2VDD is C1 which has a higher capacitance to hold more charge up to VDD to be distributed to the output, once the capacitor charge is near VDD the input pulse can switch to high which will change the bottom of the capacitor from 0v to VDD because of the inverter right below it and since Capacitors take time to release their charge and it is not an instantanious process, instead of it going from 0v to VDD across, the voltage will go from VDD to 2VDD across the capacitor, since the voltage of VDD is added with the stored charge of the capacitor which should be around VDD resulting in VDD+VDD = 2VDD.

- Output
The final inverter has its PMOS transistor gate open when the input is High, this size of the PMOS needs to be large enough to drive the larger current coming in from the C1 Capacitor, then the input is low the PMOS is off and instead the nmos pulls the output to gnd ensuring the ouput oscilates from 0 to 2VDD.

Design Limitations and Considerations:

- Input Capacitance Constraint < 100fF

We must calculate the capacitance of the initial CMOS inverter to do this we can use the equation.

Cin = Cox' * (Wn * Ln + Wp * Lp)

For our Circuit & Inverter:

Cox' = 2.5fF/um^2

Wn = 12um (NMOS width)

Wp = 12um (PMOS width)

L = 600n (NMOS & PMOS length respectively)

So our input capacitance ends up being 36fF which is under the 100fF restriction thus it meets the requirements.

- Driving 0 to 1 pF capacitor and 4.5 to 5.5VDD range

Driving a Capacitor will lower Vout in accordance to how big the capacitance is, since in our design the output minimum is 7v we must ensure that driving the capacitance of 1pF won't lower our output below 7v.

Two components that control Vout are C0 and C1, C0's capacitance determines how much time C1 gets to charge and C1 holds charge of VDD to be doubled to 2VDDWe can use:
Vf=CR/(CR+CL) * VDD *2
To ensure the Vf Voltage is above 7V
Since our VDD is 4.5 to 5.5 its best to plug in multiple values for VDD and ensure the output does not go below 7v when High.
(NOTE: Always good to add extra room for error so our C1 Cap will be slightly higher than needed)

- Input Logic Low and High Limits

For this circuit 0-1v must be considered as input low and 3-5v must be considered as input high, for this to occur we must alter the width ratio of the

initial NMOS PMOS Inverter, to lower the minimum required input max voltage to accept at least 3v as input high we must increase Beta(N) which simply means as the NMOS width increases against the PMOS the lower Vin has to be to activate the inverter. Having the width of both NMOS and PMOS be 12u case a value where with 5.5vdd the switching point was still below 3v for voltage high while maintaining 1v as LOW. Switching point can be calclualted by the following formula

Vsp = (sqrt(Bn/Bp*VTHN+(VDD-VTHP))/(1+sqrt(Bn/Bp))

Our values are:

Rn' = 20k

Rp' = 40k

Cox' = 2.5fF/um^2

Wn=Wp=12um

L=0.6um

Which provides sufficient room switching point of 3v for HIGH.

- 4ns Maximum Transition Time

The transition delay is based on the load capacitance and the sizes of the NMOS and PMOS transistors on the inverter, in this design the delay max is 4ns.
Since we are expected to support a 1pF load that will be Cl
This will be based on the output inverter which holds these values:
Ln = 0.6um
Wp = 24um
Wn = 12un
Rp = 40k
Rn = 20k
Cl = 1pF
tr = 2.2*1k*1pF= 2.2ns which is below the 4ns requirement
Also important to make the N1 transistor wide enough as that reduces resistence which reduces delay.

- Other considerations

Transistor sizing:
It is important for transistors to be large enough to drive enough current through them this is especially important for the PMOS in the output inverter as it has to drive 2VDD to the output, with its width also reducing resistance which reduces the delay. However Sizing it too large will increase the capacitance which is why the input inverter cannot have NMOS and PMOS transistors that are too large to keep the input capacitance low and waste power. But also having greater width can decrease resistence which will in turn reduce delay in most cases so it important to consider it on a case by case basis.

Capacitor Sizing:

In this design I opted to use MOSFET's in strong inversion as the capacitance to have a more compact layout size. Strong inversion requires that VGS being greater than VTH, electrons will become attracted together and short the drain which will result in a plate forming for a capacitor.
The capacitance per area is greater than a poly capacitor, this is because MOSFETs

Cox'(2.5/um^2) capacitance per area is much higher than the poly capacitor's.

C0 = 1.1pF = 2.5fF/um^2 * Wl * Wn

Wn & Wl=~ 21um;

C1 = 9pF = 2.5fF/um^2 *Wl um * Wn

Wn & Wl = 60um

Inverter 2 Sizing:

Since inverter 1 takes care of the 1v max LOW extreme and the 3v min HIGH extreme the switching point can be set to 2.5V as that is half of

our standard VDD.

Simulatons:

Input Inverter:

We Ensured this is <100fF capacitance and lowered its switching point to below 3v so it works with 0-1v low and 3v-5v high earlier in the report.

inv

This is our sim Circuit for the first inverter:

During Normal Operation the inverter Runs Smoothly

inv_norm_inp

When simming we can see the extremes of 1vin max of low to 3vin min of high does register as a output high VDD and output Low as expected and in turn this means the entire circuit will operate within the range of 0-1vin LOW and 3-5vin HIGH which meets the requirements.

ext

Main Circuit: Non-Inverting Buffer:

Second Inverer Schematic, the input inverter schematic can be found earlier in the report:

Lets do an Ideal Condition Simulation:

Sim Circuit

VDD: 5v Vin 0v-5v Load Cap = 0pF

ideal

VDD: 5.5v Vin 0v-5v Load Cap = 0pF

5.5vdd

VDD: 4.5v Vin 0v-5v Load Cap = 0pF

4.5vdd sim

Now Lets try with a Load Capacitor:

1pf load sim

Lets take a look at our delay with this 1pF load:
As we see here out Vout is above 7v before the 4ns delay mark thanks to having a wide enough transistor that reduces the resistent and thus also the delay.
delay