Lab 6 - ECE 421L 

Authored by Anthony Peytchev,

Email: peytchev@unlv.nevada.edu

10/19/2023

  

Pre-Lab

Finish Tutorial 4

NAND Gate Schematic:

nand schematic

NAND Gate Symbol:


NAND Gate Symbol


Layout:
Nand Gate Layout

DRC:

nand drc

LVS:

lvs



Lab 6

NAND GATE:


Schematic:
NAND Schematic

Symbol:
Symbol NAND

Layout:

NAND Layout

DRC:
DRC

LVS:
LVS

Simulation:
00
00
01
01
10
10
11
11
XOR GATE:

Schematic:
xor schematic

Symbol:

xor symbol

Layout:

layout

DRC:

drc

LVS:

lvs

Simulation:

00

00

01
01
10
10
11
11

Full Adder:

Schematic:

adder schem

Symbol:

schematic

Layout:

DRC:

LVS:

Conclusion:



return