Lab 2 - ECE 421L 

Authored by Anthony Peytchev,

Email: peytchev@unlv.nevada.edu

9/5/2023

  

Pre-Lab

Download Lab2.zip

Upload zip to CMOSedu directory in the ssh cadence server

type:

cd CMOSedu

then:

unzip Lab2.zip

 

Then go to library manager and navigate to lab2

open cell view of sim_Ideal_ADC_DAC

Run the sim (Launch the ADE, Session -> Load State -> Cellview -> OK, press the green start button)

Simulation ADC-DAC


adc-dac sim


Vin is a AC wave that gets converted to a Digital 10 bit value with the ADC in relation to the 5v which divides the 5v to 1048 different possible digital values in which each bit is b[0] to b[9] that gets sent to the DAC which outputs the binary value to analogue but since it is split up to 255 discrete possibilites there will be bumps in the digital wave.


dac_adc circuit


Lab 2 Report:


In this lab, we are given the task of building and simulating a 10-bit dac. The figure below shows the circuit that we will utilize to create out DAC.

Here is a 10k n-well resister I created and that will be utilized in this lab.

10k n-well res



Creating a voltage divider circuit which will be used to create our symbol. (The 2 resisters replicate 2R)

voltage divider

We then go to create -> Cellview -> From_Cellview...

Here is how the symbol is set

1 bit dac

Combining this we can make a 10 bit dac as seen below

10 bit dac

Now we can create the symbol again for the 10-bit dac

10 bit dac



10-bit DAC resistance calculation:

We ground every bit value B[9:0] and combine parallel resisters which results in 2R becoming R which is then in series making 2R. Working this method up it will leave it with a resistence of R.

Delay Calculation:


The Delay is due to drive loading, adding a 10pF capacitor will add a delay.
This will result with an RC circuit in which R is 10k and C is 10pf

td = 0.7RC

td = 0.7RC * 10K *10pF = 70ns

Here is a sim

sim

Here is the idea DAC added to the adc, the added 10K resister matches the internal 10k resistance of the dac which creates a voltage divider and will decrease the  output voltage  by half.

dacc

Here is the simulation:
sims

Here is the adc-dac with the 10pf capacitor which creats a delay in vout, decreases the output and smooths it out.:

w cap

With the resister and the capacitor which decreases the output even further.

rc

Here is the simulation to back it up:
sim

Backing Up My Work:

Zip up work every 20-30min and email it to myself


return