Final Lab Project - ECE 421L 

Authored by Baylee Perera, pererb1@unlv.nevada.edu

November 22, 2023

 

Non-inverting Buffer

 

Project: Design a non-inverting buffer circuit that presents less than 100fF input capacitance to on-chip logic and that can drive up to a 1pF load with output voltages greater than 7V (an output logic 0 is near ground and an output logic 1 is greater than 7V). Assume VDD is between 4.5V and 5.5V, a valid input logic 0 is 3V or more. Show that your design works with varying load capacitance from 0 to 1pF. Assume the slowest transition time allowed is 4ns.

 

Calculations:

Inverter Calculations:The first step was to find the specifications that were going to be needed for the nmos and pmos transistors used to make up our inverter. I started off by using a fairly common 2k resistor for my Rn value, however, it had exceeded the time constraint of 4 ns by 0.4 ns. Thus I decided to cut it in half by using a 1.5k instead. While solving this, I also had to make sure that our Input Capacitance stayed under 100fF. 
Check:Once I had the calcultations found above, I moved onto making sure that my mosfet capacitors were going to be correct on which was going to be greater than the other. 
MOSFET Capacitor:
This work here helps to prove the above work to be true. This showing that our mosfet capacitor on the right handside is larger than our mosfet capacitor on the left hand side.
Schematic:
This is the end result of my Non-inverting Buffer once I finished calculating for the different nmos and pmos components.
 
Simulations:
Symbol:
Sim Schematic for capacitance sweep: 
Parametric Set:
Capacitance Sweep:
Sim Schematic for voltage sweep:
Voltage sweep; 4.5V, 5V, 5.5V:
 
The above screensshots help to prove when we do our capactiance sweep that our voltage output is going to be greater than 7V. This even proves to be true when we do our voltage sweep of 4.5V, 5V, and 5.5V with a 1pF capactiance with the output that the simulation will still output at 7V.

Layout:
Updated Schematic:In order for the LVS to match, I had to update the schematic so that N0, N1, N2 and N3's bodies are tied to ground.
Layout:
Zoomed in Layout:

DRC: 
Extracted:
LVS:
 

Lab backup:

lab_project

Return