Lab 6 - ECE 421L 

Authored by Baylee Perera, pererb1@unlv.nevada.edu

October 25, 2023

Design, Layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder

Prelab:

We always start by making sure we have back ups of our previous labs. The prelab for this lab is following the steps of Tutorial 4, which focuses on how to build a NAND gate.

Layout of NAND gate
LVS before changing the LVS rules
Changes made to LVS rule
LVS after changing the LVS rules	Somehow my netlist is successfully matching after I've changed my LVS rule's and I'm not really sure how. I followed the instructions of the prelab.

In this lab, we will be designing multiple layouts and schematics with components of nmos and pmos transitors. After building out NAND gate and XOR gate, we will then use both of them to build a Full Adder.

NAND Gate:

The first step of the lab procedure, we will be making a 2-input NAND Gate schematic and layout a size of 6u/0.6u.

Schematic
Symbol
Layout/DRC
Extracted
LVS Check

XOR Gate:

Next we will take our knowledge from the NAND gate to build a 2-input XOR gate.

Schematic
Symbol
Layout/DRC
Extracted
LVS Check

Truth Table:

 We will use the truth table below to help prove that our logic gates do indeed perform logic based inputs. 

The schematic and simulation below shows what is going on. The simulations show that we are getting the expected results for the logic outputs. The bumps in the simulation are from the rise and fall times for each device.

Schematic
Simulation

Full Adder Gate:

We will now use both the NAND gate and XOR gate we made to make our Full Adder design.

Schematic
Symbol
Layout/DRC
Extracted
LVS Check
Schematic
Simulation	I think I have my voltage inputs wrong and that's why I am not getting the correct output.

Lab backups:

lab6

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