Lab 2 - EE 421L

Design of a 10-bit DAC 

Authored by Isabella Paperno, paperi1@unlv.nevada.edu

Start date: 09/05/2023

Due date: 09/13/2023

Pre-lab work:

• Back-up all of your work from the lab and the course.
• Read through this entire lab write-up before doing the pre-lab.
• Download lab2.zip to your desktop.
• This archive contains a simulation example using an ideal 10-bit Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC).
• Upload this zip file to the design directory on the server that you are running Cadence from, e.g., Tutorial_1, CMOSedu, etc.
• Note that it's assumed you are using the NCSU Cadence Design Kits.

• Unzip this directory using unzip lab2.zip and add, to your cds.lib in the design dierctory, the following statement (assuming the design directory is CMOSedu):
• DEFINE lab2 $HOME/CMOSedu/lab2

• Start Cadence from the design directory
• Use the Library Manager and navigate to the lab2 Library.

• Open the schematic view of the cell sim_Ideal_ADC_DAC.
• This cell contains the ideal 10-bit ADC and DAC as seen below.

• Run the simulation (Launch the ADE, Session -> Load State -> Cellview ->OK, press the green start button) to get the results seen in the second image below.
• Make sure you understand how to change the background color, line thickness, and type of line (e.g. solid, dashed, etc.)

   
To calculate the least significant bit (LSB), we can use the equation provided in Fig. 30.14 from the CMOS book: 1 LSB = VDD/2^N
Should I want to find the LSB calculation of the DAC in Fig. 30.14 I would use 5 for N and could pick any VDD such as 5V.
However if I wanted to find the LSB calculation of the Ideal_DAC and compare it with the simulation results, I would use 5V as VDD and 10 as N, for the 10-bit DAC.

Through this hand-calculation, I found the LSB for a 10-bit DAC with VDD at 5V to be 4.88mV.

• Prior to coming to lab make sure you understand how the input voltage, Vin, is related to B[9:0] and Vout (the quiz may ask a question about this).
• In your lab report: 
1. Provide narrative of the steps seen above, 
2. Provide, and discuss, simulation results different from the above to illustrate your understanding of the ADC and DAC, 
3. Explain how you determine the least significant bit (LSB, the minimum voltage change on the ADC's input to see a change in the digital code B[9:0]) of the converter. 
• Use simulations to support your understanding.
• Backup your webpages and design directory.

Lab description:

We will use n-well resistors to implement a 10-bit DAC based upon the components used in Fig. 30.14 from the CMOS book (seen below). The inputs to the DAC come from the ADC found on the left side of the 2R resistors.

Lab procedures:

Creating schematics and symbols: 

I first started the lab by creating a 10k n-well resistor (voltage divider). Since this required 2R along the input wire, I made sure to implement it using two separate 10k resistors in series. Now, this voltage divider can act as 1-bit needed for the 10-bit DAC.

This was then converted into a symbol with an input, output, and an inout connection for the next bit. This next_bit inout connection will be used for connecting multiple 1-bit symbols to create the 10-bit DAC.

Now that the 1-bit symbol is completed, I can begin working on the 10-bit DAC. I created a new schematic where I added 10 of the 1-bit connectors and wired them all together to create the 10-bit DAC. The top-right connection represents bit 9 and is connected to the output while the bottom-left connection represents bit 0 and is connected to ground with a 10k resistor in between. A closer view of the bottom half of the 10-bit DAC is besides (to the right of) the full image.

The 10k resistor underneath the b0 connection is necessary to ensure that the 10-bit DAC has 2R going out to ground.

Finally, a symbol can be created for the 10-bit DAC.

Hand Calculations:

Now that the 10-bit DAC is finished, it needs to be tested to check if it was done correctly. For this test, all inputs except B9 have been grounded and B9 is connected to a pulse source (0 to VDD). To verify it was done correctly, I will preform hand calculations to compare the simulation results to.

I have drawn out the pathing of the voltage under the specified condition above and found that the output voltage is expected to be half of the input voltage. I have also preformed hand calculations to predict the output of this 10-bit DAC using 0.7RC to find the delay of the DAC when it has a 10pF load and found it to be 70ns.

Simulations: 

This first simulation will performing under the same conditions as the hand calculations to check the validity of the 10-bit DAC. Again, the conditions are that all inputs except B9 have been grounded and B9 is connected to a pulse source (0 to VDD). For the sake of the simulation, I chose VDD to be 5V.

This simulation confirms my hand calculations that, with everything except B9 grounded, the output voltage is half of the input voltage as the 2.5V output is exactly half of the 5V input.

Now that I know my 10-bit DAC works properly, I can connect it to the provided Ideal ADC component and run the provided simulation.

When I tried running the given simulation I ran into a few errors so I had to force the simulation to converge by going into the ADE Simulation -> Options -> Analog and setting the values as seen below.

Once that was completed I still had errors running the simulation. So I ended up changing the VDD from 5V to 4.99V, changing my schematic as seen below.

Then I was able to successfully run the provided simulation and obtained the following outputs, which match the outputs from the Ideal DAC simulation performed in the prelab.

Next, I added a 10k resistive load to the output of the previous schematic and ran the same simulation. 

Here, I am expecting the output voltage to be half of the input voltage as seen in my hand calculations.

And these results display exactly what was predicted: the output voltage is exactly half of the input voltage.

Then I replaced the 10k resistive load with a 10pF load.

Here, I am expecting the output voltage to lag behind the input voltage by 70ns as seen in my hand calculations.

Finally, I am testing both the 10k resistive load and 10pF load in parallel with each other.

With this, I am expecting both of the previous results to occur simultaneously.

And this graph does resemble the expected results. The output voltage is just about half of the input voltage and is lagging behind by about 70ns.

Questions: 

• Explain what happens if the DAC drives a 10k load.

• In a real circuit the switches seen above (the outputs of the ADC) are implemented with transistors (MOSFETs).
• Discuss what happens if the resistance of the switches isn't small compared to R.

Backing Up Lab Work:

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