Lab 5 - ECE 421L 

Authored by Ronnie Moran, moranr1@unlv.nevada.edu

Today's date: 10/10/23

Prelab

Tutorial 3 Work:

DRC and LVS

Lab Work:

First Inverter (m=1)

Here is the schematic, symbol, extracted, and layout of my 12u/6u inverter.

Here is the DRC and LVS of the following layout shown above:

Simulation Results:

Second Inverter (m=4)

Here is the schematic, symbol,extracted, and layout of my 48u/24u inverter.

Here is the DRC and LVS of the layout shown above:

Simulation Results:

Spectre

UltraSim

I backed up my work as directed in the prelab steps. The zip file is in the previous directory.