Lab 6 - ECE 421L
Authored
by Ronnie Moran, moranr1@unlv.nevada.edu
Today's
date: 10/28/23
Prelab:
The Prelab work this lab was to follow tutorial 4 and show our results.
Here is my schematic of my NAND gate:
![](Lab%20Pictures/labs1.PNG)
Symbol View:
![](Lab%20Pictures/prelab2.PNG)
Layout with DRC/LVS:
![](Lab%20Pictures/prelab3.png)
![](Lab%20Pictures/labs4.PNG)
Lab Work:
In this lab we will be designing a NAND gate, XOR gate, and a Full adder.
This means each design will have a corresponding symbol, layout, and simulations.
1. NAND Gate:
Here is my schematic for the NAND gate which I will make a symbol from this cellview.
![](Lab%20Pictures/labs1.PNG)
Symbol View:
![](Lab%20Pictures/labs2.PNG)
Simulation of the NAND gate:
![](Lab%20Pictures/labs6.PNG)
Layout with DRC/LVS of the nand gate similar to the one in the prelab nut not quite:
![](Lab%20Pictures/labs3.PNG)
![](Lab%20Pictures/labs4.PNG)
2. XOR Gate:
Here is my schematic for the XOR gate which I will make a symbol from this cellview.
![](Lab%20Pictures/labs7.PNG)
Here is the symbol view:
![](Lab%20Pictures/labs8.PNG)
Simulation of the XOR gate:
![](Lab%20Pictures/labs11.PNG)
Here is the layout of my XOR gate with LVS/DRC
![](Lab%20Pictures/labs9.PNG)
![](Lab%20Pictures/labs10.PNG)
![](Lab%20Pictures/labs19.PNG)
3. Full-Adder:
Here is my schematic for the Full-Adder:
![](Lab%20Pictures/labs17.PNG)
Here is my symbol for the Full-Adder
![](Lab%20Pictures/labs12.PNG)
Simulation of the Full-Adder:
![](Lab%20Pictures/labs14.PNG)
Here is the layout of my Full-Adder with LVS/DRC
![](Lab%20Pictures/labs18.png)
![](Lab%20Pictures/labs13.PNG)
![](Lab%20Pictures/labs16.PNG)
Return to EE 421 Labs