Lab

Lab 7 - ECE 421L

Authored by Benjamin Molina, molinb1@unlv.nevada.edu

11/7/2023

Prelab Description:

The prelab involves students backing up the work they've done from previous labs which has been done. Tutorial 5 must also be covered which goes over the design and simulations of a ring oscillator.

Ring Oscillator Design:	Simulation without initial condition:

Simulation with initial condition set to "0":	Concise schematic and simulation:

Ring Oscillator Layout:	Ring Oscillator Extracted:

LVS:	Ring Oscillator Symbol Simulation:

Now that we've completed the tutorial and understand the way we can use buses to create concise schematics for components that handle multiple bits, we can begin the main part of the lab.

Lab description:

The contents of this lab include creating several logic gates for multiple bits, the construction of a MUX/DEMUX component to create an 8-bit MUX/DEMUX later, and finally to create an 8-bit full adder device.

-4-bit Inverter:
First need to design a simple 4-bit inverter. We could achieve this with 4 seperate inverters, however that is not that efficient nor concise. By using what we learned in Tutorial #5 we can create a more condensed circuit.

Schematic	Symbol

4-bit Schematic	4-bit Simulation

Here we can see that the varying capacitors affect the RC delay of the rise and fall time. We generally don't like having these delays for inverters since we want voltage to change instantly.

-8-bit Logic Gates:
Now we need to construct 8-bit logic gates. We should have a schematic, symbol and simulation for each gate. Now the simulations need to only simulate one bit of the 8 to save time.

	8-bit Schematic	8-bit Symbol	CMOS Schematic
NAND
AND
NOR
OR
NOT

For the construction of the AND and OR gates we used the schematic of the NAND and NOR gates and added an inverter at the end to make things easier. Now we will simply simulate the outputs of the gates all at once.

Here we only simulate one bit for an output since all the output bits will be the same. Normally we'd attach capacitors as load for each bit output to see how they affect the RC delays but for now we will simply do this.

-MUX/DEMUX:
Using the symbol and the schematic of the MUX provided we now build a simulation to check our understanding of how it works.

Schematic:	Simulation:

Now all we need to do is create an 8 bit version of the MUX/DEMUX component using the techniques used above and simulate the output.

MUX/DEMUX Schematic	Symbol

Now using this symbol we can create a simulation for the 8-bit MUX and DEMUX.

8-Bit MUX	8-Bit MUX Simulation

8-Bit DEMUX	8-Bit DEMUX Simulation

-Full Adder:
Finally all we have left to do is design a full adder and then create a concise schematic for the 8-bit variant. We also must make a layout for this part of the lab.

Full Adder CMOS Schematic

8-Bit Adder Schematic

8-Bit Symbol

Below the layout for the full adders designed will be showed.

1-Bit Full Adder/DRC	Extracted 1-Bit Full Adder

8-Bit Full Adder	Extracted 8-Bit Adder

LVS for 1 Full Adder:

Now it is rather difficult to see the full view of the 8-bit adder, so below is a picture emphasizing the connection between the 8 adders that are tied together. Importantly we can see that the Cout of one gate goes into the Cin of the other and this contiues until the end whe we reach Cout<7>.

LVS for 8-Bit Full Adder:

Now all that remains is to simulated the Full Adder:

Schematic	Simulation

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As always work has been backed up and saved on Mac folder outside of main computer.

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